[BOOK][B] The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches
P Jespers - 2009 - books.google.com
IC designers appraise currently MOS transistor geometries and currents to compromise
objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc …
objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc …
An LDE-Aware gm/ID-Based Hybrid Sizing Method for Analog Integrated Circuits
T Liao, L Zhang - … Transactions on Computer-Aided Design of …, 2020 - ieeexplore.ieee.org
Layout-dependent effects (LDEs) have become increasingly more important in the synthesis
of analog integrated circuits. In this article, a two-phase hybrid sizing method for high …
of analog integrated circuits. In this article, a two-phase hybrid sizing method for high …
Sizing of multi-stage Op Amps by combining design equations with the gm/ID method
G Shi - Integration, 2021 - Elsevier
Analog integrated circuit design has as integral parts both analytical reasoning and
numerical validation in the process from topology construction to sizing. Given a circuit …
numerical validation in the process from topology construction to sizing. Given a circuit …
Operating-point driven formulation for analog computer-aided design
I Guerra-Gómez, T McConaghy… - Analog Integrated Circuits …, 2013 - Springer
In designing analog integrated circuits, the step of selecting device sizes and biases is
crucial to enhance the final performance, power, and yield of the circuits. In manual design …
crucial to enhance the final performance, power, and yield of the circuits. In manual design …
Parasitic-aware gm/ID-based many-objective analog/RF circuit sizing
T Liao, L Zhang - 2018 19th International Symposium on …, 2018 - ieeexplore.ieee.org
Accurate parasitic consideration in analog/RF circuit synthesis becomes more essential
since layout-dependent effects become more influential in the advanced technologies. In …
since layout-dependent effects become more influential in the advanced technologies. In …
Efficient Parasitic-aware gm/ID-based Hybrid Sizing Methodology for Analog and RF Integrated Circuits
T Liao, L Zhang - ACM Transactions on Design Automation of Electronic …, 2020 - dl.acm.org
As the primary second-order effect, parasitic issues have to be seriously addressed when
synthesizing high-performance analog and RF integrated circuits (ICs). In this article, a two …
synthesizing high-performance analog and RF integrated circuits (ICs). In this article, a two …
Novelty search for the synthesis of current followers
E Naredo, MA Duarte-Villasenor… - Computación y …, 2016 - scielo.org.mx
A topology synthesis method is introduced using genetic algorithms (GA) based on novelty
search (NS). NS is an emerging meta-heuristic, that guides the search based on the novelty …
search (NS). NS is an emerging meta-heuristic, that guides the search based on the novelty …
Input offset cancellation trimming technique for operational amplifiers
AR Mohamed, MF Ibrahim… - 2013 Saudi International …, 2013 - ieeexplore.ieee.org
This paper presents a novel input offset cancellation technique dedicated for analog
building blocks. This technique provides an injected current to the analog input signal that is …
building blocks. This technique provides an injected current to the analog input signal that is …
Design and Implementation of Operational Amplifiers with CMOS 180 nm Technology Node using gm/ID Methodology
P Saravanan, R Deepakraj… - 2023 IEEE 20th India …, 2023 - ieeexplore.ieee.org
This work deals with the design procedures for single stage and two stage operational
amplifiers with CMOS 180 nm technology node using gm/ID methodology. The gm/ID …
amplifiers with CMOS 180 nm technology node using gm/ID methodology. The gm/ID …
Analog circuits sizing using multi-objective evo-lutionary algorithm based on decomposition
M Nohtanipour, MH Maghami… - Informacije MIDEM, 2021 - ojs.midem-drustvo.si
Several analog circuit design has been suggested where a layout generator is used after a
circuit sizing. But, many iterations between circuit sizing and layout generator stages are …
circuit sizing. But, many iterations between circuit sizing and layout generator stages are …