During the last two decades, wireless communication has been revolutionized by near-
capacity error-correcting codes (ECCs), such as turbo codes (TCs), which offer a lower bit …

The power consumption of integrated circuits is one of the most problematic considerations
affecting the design of high-performance chips and portable devices. The study of power …

A 24Mb/s 3GPP-HSDPA radix-4 logMAP turbo decoder is designed for 3G data terminals. It
features an approximate radix-4 logsum circuit to achieve 145MHz operation. Power is …

Turbo codes have recently been considered for energy-constrained wireless communication
applications, since they facilitate a low transmission energy consumption. However, in order …

Mobile wireless terminals tend to become multimode wireless communication devices.
Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware …

The turbo decoder is the most challenging component in a digital HSDPA receiver in terms
of computation requirement and power consumption, where large block size and recursive …

Circuits and an IC implementation of a four-state, block length 16, three-metal one-poly 0.35-
μm CMOS analog turbo decoder with a fully programmable interleaver are presented. The …

A 6 to 75.6 Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4,
5.35/spl mu/s/block decoding latency and up to 8.25 dB coding gain is described. This IC is …

Future mobile and wireless communication networks require flexible modem architectures to
support seamless services between different network standards. Hence, a common …

This work presents the design and the test results of an analog decoder for the 40-bit block
length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated …