Graph processing is typically memory bound due to low compute to memory access ratio
and irregular data access pattern. The emerging high-bandwidth memory (HBM) delivers …

Sparse linear algebra operators are memory bound due to low compute to memory access
ratio and irregular data access patterns. The exceptional bandwidth improvement provided …

While systolic arrays are widely used for dense-matrix operations, they are seldom used for
sparse-matrix operations. In this paper, we show how a systolic array of Multiply-and …

Dynamic adaptation is a post-silicon optimization technique that adapts the hardware to
workload phases. However, current adaptive approaches are oblivious to implicit phases …

Machine learning (ML) and high-performance computing (HPC) applications increasingly
combine dense and sparse memory access computations to maximize storage efficiency …

With the end of Dennard scaling and Moore's law, it is becoming increasingly difficult to build
hardware for emerging applications that meet power and performance targets, while …

We present Versa, an energy-efficient 36-core systolic multiprocessor with dynamically
reconfigurable interconnects and memory. Versa leverages reconfigurable functional units …

This article reports a passive analog feature extractor for realizing an area-and-power-
efficient voice activity detector (VAD) for voice-control edge devices. It features a switched …

Hardware acceleration of Artificial Intelligence (AI) workloads has gained widespread
popularity with its potential to deliver unprecedented performance and efficiency. An …

We present domain adaptive processor (), a programmable systolic-array processor
designed for wireless communication and linear algebra workloads. uses a globally …