Neurosymbolic programming

S Chaudhuri, K Ellis, O Polozov, R Singh… - … and Trends® in …, 2021 - nowpublishers.com
We survey recent work on neurosymbolic programming, an emerging area that bridges the
areas of deep learning and program synthesis. Like in classic machine learning, the goal …

A review of literature on parallel constraint solving

IP Gent, I Miguel, P Nightingale… - Theory and Practice of …, 2018 - cambridge.org
As multi-core computing is now standard, it seems irresponsible for constraints researchers
to ignore the implications of it. Researchers need to address a number of issues to exploit …

SAT solving with GPU accelerated inprocessing

M Osama, A Wijs, A Biere - … Conference on Tools and Algorithms for the …, 2021 - Springer
Since 2013, the leading SAT solvers in the SAT competition all use inprocessing, which
unlike preprocessing, interleaves search with simplifications. However, applying …

Certified SAT solving with GPU accelerated inprocessing

M Osama, A Wijs, A Biere - Formal Methods in System Design, 2024 - Springer
Since 2013, the leading SAT solvers in SAT competitions all use inprocessing, which, unlike
preprocessing, interleaves search with simplifications. However, inprocessing is typically a …

Cud@ sat: Sat solving on gpus

A Dal Palù, A Dovier, A Formisano… - Journal of Experimental …, 2015 - Taylor & Francis
The parallel computing power offered by graphic processing units (GPUs) has been recently
exploited to support general purpose applications–by exploiting the availability of general …

Hardware accelerated SAT solvers—A survey

AA Sohanghpurwala, MW Hassan, P Athanas - Journal of Parallel and …, 2017 - Elsevier
Boolean Satisfiability (SAT) is a problem that holds great importance both theoretically and
in practical applications. Although the general SAT problem is NP-complete, advancements …

Survey of machine learning for software-assisted hardware design verification: Past, present, and prospect

N Wu, Y Li, H Yang, H Chen, S Dai, C Hao… - ACM Transactions on …, 2024 - dl.acm.org
With the ever-increasing hardware design complexity comes the realization that efforts
required for hardware verification increase at an even faster rate. Driven by the push from …

Automated design error debugging of digital VLSI circuits

M Moness, L Gaber, AI Hussein, HM Ali - Journal of Electronic Testing, 2022 - Springer
As the complexity and scope of VLSI designs continue to grow, fault detection processes in
the pre-silicon stage have become crucial to guaranteeing reliability in IC design. Most fault …

Fault detection based on deep learning for digital VLSI circuits

L Gaber, AI Hussein, M Moness - Procedia Computer Science, 2021 - Elsevier
As growing complexity of digital VLSI circuits, fault detection and correction processes have
been the most crucial phases during IC design. Many CAD tools and formal approaches …

Weighted model counting on the GPU by exploiting small treewidth

JK Fichte, M Hecher, S Woltran… - 26th Annual European …, 2018 - drops.dagstuhl.de
We propose a novel solver that efficiently finds almost the exact number of solutions of a
Boolean formula (# Sat) and the weighted model count of a weighted Boolean formula …