Artificial intelligence (AI) edge devices prefer employing high-capacity nonvolatile compute-
in-memory (CIM) to achieve high energy efficiency and rapid wakeup-to-response with …

Low-power Al edge devices should provide short-latency (T_WK-RP) and low-energy
(E_WK-RP) wakeup responses from power-off mode to handle event-triggered computing …

Extreme edge devices or Internet-of-Things (IoT) nodes require both ultra-low power (ULP)
always-on (AON) processing as well as the ability to do on-demand sampling and …

DNN workloads can be scheduled onto DNN accelerators in many different ways: from layer-
by-layer scheduling to cross-layer depth-first scheduling (aka layer fusion, or cascaded …

On-chip non-volatile compute-in-memory (nvCIM) enables artificial intelligence (AI)-edge
processors to perform multiply-and-accumulate (MAC) operations while enabling the non …

Artificial intelligence (AI) edge devices increasingly require the enhanced accuracy of
floating-point (FP) multiply-and-accumulate (MAC) operations as well as nonvolatile on-chip …

Applications of machine learning (ML) increasingly penetrate into our daily routines, our
work, and our living environments. In this way, more complex machine intelligence …

Optimal deployment of deep neural networks (DNNs) on state-of-the-art Systems-on-Chips
(SoCs) is crucial for tiny machine learning (TinyML) at the edge. The complexity of these …

Emerging deep neural network (DNN) applications require high-performance multi-core
hardware acceleration with large data bursts. Classical network-on-chips (NoCs) use serial …

With the widespread adoption of edge AI, the diversity of application requirements and
fluctuating computational demands present significant challenges. Conventional …