Analog integrated circuit routing techniques: An extensive review

RMF Martins, NCC Lourenço - IEEE Access, 2023 - ieeexplore.ieee.org
Routing techniques for analog and radio-frequency (A/RF) integrated circuit (IC) design
automation have been proposed in the literature for over three decades. On those, an …

Recent research development and new challenges in analog layout synthesis

MPH Lin, YW Chang, CM Hung - 2016 21st Asia and South …, 2016 - ieeexplore.ieee.org
Analog and mixed-signal integrated circuits play an important role in many modern
emerging system-on-chip (SoC) design applications. With the expansion of the markets of …

Performance-driven analog layout automation: Current status and future directions

P Xu, J Li, TY Ho, B Yu, K Zhu - 2024 29th Asia and South …, 2024 - ieeexplore.ieee.org
Optimizing circuit performance presents a pivotal challenge in the realm of automatic analog
physical design. The intricacy of analog performance arises from its sensitivity to layout …

CAD for Analog/Mixed‐Signal Integrated Circuits

AF Budak, DZ Pan, H Chen, K Zhu… - Advances in …, 2022 - Wiley Online Library
While digital integrated circuits (ICs) has adopted highly automated computer aided design
(CAD) tools for decades including synthesis, placement, and routing, analog, and mixed …

Non-uniform multilevel analog routing with matching constraints

HC Ou, HCC Chien, YW Chang - Proceedings of the 49th Annual Design …, 2012 - dl.acm.org
Symmetry, topology-matching, and length-matching constraints are three major routing
considerations to improve the performance of an analog circuit. Symmetry constraints are …

A DAG-based algorithm for obstacle-aware topology-matching on-track bus routing

CH Hsu, SC Hung, H Chen, FK Sun… - Proceedings of the 56th …, 2019 - dl.acm.org
As clock frequencies increase, topology-matching bus routing is desired to provide an initial
routing result which facilitates the following buffer insertion to meet the timing constraints …

Low power robust FinFET-based SRAM design in scaled technologies

SK Gupta, K Roy - Circuit design for reliability, 2014 - Springer
FinFETs have emerged as alternatives to conventional bulk MOSFETs in scaled
technologies due to superior gate control of the channel, lower short channel effects and …

A fast prototy** framework for analog layout migration with planar preservation

PC Pan, CY Chin, HM Chen, TC Chen… - … on Computer-Aided …, 2015 - ieeexplore.ieee.org
Analog layout generation in the advanced CMOS design is challenging by its increasing
layout constraints and performance requirements. This situation becomes more intricate by …

Configurable analog routing methodology via technology and design constraint unification

PC Pan, HM Chen, YK Cheng, J Liu… - Proceedings of the …, 2012 - dl.acm.org
In this paper, we present a novel configurable analog routing methodology for more efficient
analog layout automation. By the help of OpenAccess constraint group format, the …

A pre-search assisted ILP approach to analog integrated circuit routing

CY Wu, H Graeb, J Hu - 2015 33rd IEEE International …, 2015 - ieeexplore.ieee.org
The routing of analog integrated circuits (IC) has long been a challenge due to numerous
constraints (such as symmetry and topology-matching) that matter for overall circuit …