A simple model that links MOSFET performance, in the form of intrinsic switch delay, to
effective carrier velocity in the channel is developed and fitted to historical data. It is shown …

Hole mobility and velocity are extracted from scaled strained-Si 0.45 Ge 0.55 channel p-
MOSFETs on insulator. Devices have been fabricated with sub-100-nm gate lengths …

Using a new extraction methodology taking into account multisubband population and
carrier degeneracy, we have experimentally determined backscattering coefficients, ballistic …

Novel uniaxially strained SiGe-on-insulator (SGOI) pMOSFETs with Ge content of 20% have
been successfully fabricated by utilizing lateral (uniaxial) strain-relaxation process on …

The hole mobility characteristics of< 110>/(100)-oriented asymmetrically strained-SiGe p-
MOSFETs are studied. Uniaxial mechanical strain is applied to biaxial compressive strained …

The combination of channel mobility-enhancement techniques such as strain engineering
with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate …

The integration of lanthanum lutetium oxide (LaLuO 3) with an value of 30 is, for the first
time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a …

In this paper, we review different CMOS technologies used at CEA-LETI to improve hole and
electron velocity for the 32 nm technology node Fully Depleted Silicon-On-Insulator (FDSOI) …

In this paper we compare two innovative approaches to the integration of Ge-channel on
Insulator MOSFETs from conventional Bulk-Si substrates. The first one is based on the Ge …

We demonstrate that planar Fully Depleted Silicon-On-Insulator (FDSOI) architectures allow
improving the electrostatic control (and in turn the dynamic performance by 22%) and the …