Spiking neural networks (SNNs) are gaining increasing attention for their biological
plausibility and potential for improved computational efficiency. To match the high spatial …

The Network on Chip (NoC) is a cost-effective alternative to bus-based connectivity in most
multi-core networks. The NoC system solves the drawbacks of bus-based networks by …

Delays caused by congestion, faults and process variation (PV) degrade networks-on-chip
(NoC) performance. A congestion aware, fault tolerant and process variation aware adaptive …

To meet the demand for high on-chip network performance, flexible routing algorithms
supplying path diversity and congestion alleviation are required. We propose a CAOE-FA …

General purpose routing techniques for a WSN cannot be capable to give adequate
functioning for various communication. This creates low adaptively provided with a general …

High‐speed router design for network on chip (HSRDN) is proposed for controlling the traffic
congestion and deadlocks. Diagonal based nearest‐path routing algorithm for NoC …

The quasi-delay-insensitive (QDI) based asynchronous network-on-chip (ANoC) has several
advantages over clock-based synchronous network-onchips (NoCs). The asynchronous …

Asynchronous router is proposed as a vigorous design to alleviate the impact of process
variation in Network on Chip (NoC). The impact of process variation on the network …

In IC design, Built-In Self-Test (BIST) integrates testing capabilities into the device,
eliminating external test equipment needs and enabling automatic chip testing. BIST is …

Due to technology scaling, achieving increasing bandwidth demands has become
challenging and has led to the preference of Network-On-Chips (NoCs) over bus …