Testing 3D chips containing through-silicon vias
EJ Marinissen, Y Zorian - 2009 International Test Conference, 2009 - ieeexplore.ieee.org
Today's miniaturization and performance requirements result in the usage of high-density
integration and packaging technologies, such as 3D stacked ICs (3D-SICs) based on …
integration and packaging technologies, such as 3D stacked ICs (3D-SICs) based on …
An industry perspective on current and future state of the art in system-on-chip (SoC) technology
TACM Claasen - Proceedings of the IEEE, 2006 - ieeexplore.ieee.org
In fast-moving consumer electronics markets where product lifetimes may be measured in
months rather than years, fast time-to-market development of the system-on-chip solutions …
months rather than years, fast time-to-market development of the system-on-chip solutions …
A structured and scalable test access architecture for TSV-based 3D stacked ICs
EJ Marinissen, J Verbree… - 2010 28th VLSI Test …, 2010 - ieeexplore.ieee.org
New process technology developments enable the creation of three-dimensional stacked
ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents …
ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents …
Test-access mechanism optimization for core-based three-dimensional SOCs
Embedded cores in a core-based system-on-chip (SOC) are not easily accessible via chip
I/O pins. Test-access mechanisms (TAMs) and test wrappers (eg, the IEEE Standard 1500 …
I/O pins. Test-access mechanisms (TAMs) and test wrappers (eg, the IEEE Standard 1500 …
Testing TSV-based three-dimensional stacked ICs
EJ Marinissen - 2010 Design, Automation & Test in Europe …, 2010 - ieeexplore.ieee.org
To meet customer's product-quality expectations, each individual IC needs to be tested for
manufacturing defects incurred during its many high-precision, and hence defect-prone …
manufacturing defects incurred during its many high-precision, and hence defect-prone …
Test-architecture optimization and test scheduling for TSV-based 3-D stacked ICs
Through-silicon via (TSV)-based 3-D stacked ICs (SICs) are becoming increasingly
important in the semiconductor industry. In this paper, we address test architecture …
important in the semiconductor industry. In this paper, we address test architecture …
3D DfT architecture for pre-bond and post-bond testing
EJ Marinissen, CC Chi, J Verbree… - … IEEE International 3D …, 2010 - ieeexplore.ieee.org
Process technology developments enable the creation of three-dimensional stacked ICs (3D-
SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D …
SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D …
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-
based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration …
based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration …
Post-bond testing of 2.5 D-SICs and 3D-SICs containing a passive silicon interposer base
Through-Silicon Vias (TSVs) enable high-density, low-latency, and low-power interconnects
for system chips that consist of multiple dies. In “2.5 D” Stacked ICs (2.5 D-SICs), multiple …
for system chips that consist of multiple dies. In “2.5 D” Stacked ICs (2.5 D-SICs), multiple …
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor
industry. In this paper, we address the problem of test architecture optimization for 3D …
industry. In this paper, we address the problem of test architecture optimization for 3D …