Configuring routing in mesh networks
L Bao, IR Bratt - US Patent 8,050,256, 2011 - Google Patents
(57) ABSTRACT A processor includes a plurality of processor tiles, each tile including a
processor core, and an interconnection network interconnects the processor cores and …
processor core, and an interconnection network interconnects the processor cores and …
Stacked memory device with metadata management
(65) Prior Publication Data Primary Examiner—Sam Rizk US 2014/004O698 A1 Feb. 6,
2014(57) ABSTRACT (51) Int. Cl A processing system comprises one or more processor ioM …
2014(57) ABSTRACT (51) Int. Cl A processing system comprises one or more processor ioM …
Energy efficient power distribution for 3D integrated circuit stack
R Saraswat, A Schaefer, S Supriyanto - US Patent 8,547,769, 2013 - Google Patents
Multiple dies can be stacked in What are commonly referred to as three-dimensional
modules (or “stacks”) With interconnections betWeen the dies, resulting in an IC module …
modules (or “stacks”) With interconnections betWeen the dies, resulting in an IC module …
Three-dimensional memory module architectures
BACKGROUND An intrinsic problem shared by all computer systems is the need for
increased main memory system performance with out a commensurate increase in energy …
increased main memory system performance with out a commensurate increase in energy …
Die-stacked memory device with reconfigurable logic
A die-stacked memory device incorporates a reconfigurable logic device to provide
implementation flexibility in performing various data manipulation operations and other …
implementation flexibility in performing various data manipulation operations and other …
Co-packaging photonic integrated circuits and application specific integrated circuits
Disclosed herein are designs, structures and techniques for advanced packaging of multi-
function photonic integrated circuits that allow such high-performance multi-function …
function photonic integrated circuits that allow such high-performance multi-function …
Configuring routing in mesh networks
L Bao, IR Bratt - US Patent 8,045,546, 2011 - Google Patents
A plurality of processor tiles are provided, each processor tile including a processor core. An
interconnection network interconnects the processor cores and enables transfer of data …
interconnection network interconnects the processor cores and enables transfer of data …
3-D stacked memory with reconfigurable compute logic
A 3D-stacked memory device including: a base die including a plurality of switches to direct
data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of …
data flow and a plurality of arithmetic logic units (ALUs) to compute data; a plurality of …
Query operations for stacked-die memory device
An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die
memory device includes a set of one or more stacked memory dies implementing memory …
memory device includes a set of one or more stacked memory dies implementing memory …
Method and system for hybrid integration of optical communication systems
T **uet, S Abdalla, M Peterson, G Masini… - US Patent …, 2016 - Google Patents
Methods and systems for hybrid integration of optical com munication systems are disclosed
and may include receiving continuous wave (CW) optical signals in a silicon photonics die …
and may include receiving continuous wave (CW) optical signals in a silicon photonics die …