An efficient algorithm for modulus operation and its hardware implementation in prime number calculation
WAS Wijesinghe - AEU-International Journal of Electronics and …, 2025 - Elsevier
This paper presents a novel algorithm for the modulus operation for FPGA implementation.
The proposed algorithm use only addition, subtraction, logical, and bit shift operations …
The proposed algorithm use only addition, subtraction, logical, and bit shift operations …
FPGA Modular Multipliers using Hybrid Reduction Techniques
Modular multiplication is a key kernel in many computing fields. What makes this function so
challenging are the very large word sizes–sometimes in the thousands of bits–that are …
challenging are the very large word sizes–sometimes in the thousands of bits–that are …
A High-Speed Hardware Algorithm for Modulus Operation and its Application in Prime Number Calculation
WA Wijesinghe - arxiv preprint arxiv:2407.12541, 2024 - arxiv.org
This paper presents a novel high-speed hardware algorithm for the modulus operation for
FPGA implementation. The proposed algorithm use only addition, subtraction, logical, and …
FPGA implementation. The proposed algorithm use only addition, subtraction, logical, and …