Classical floorplanning minimizes a linear combination of area and wirelength. When
simulated annealing is used, eg, with the sequence pair representation, the typical choice of …

In this paper, we propose a transitive closure graph-based representation for general
floorplans, called TCG, and show its superior properties. TCG combines the advantages of …

Abstract In [1], Murata et al introduced an elegant representation of block placement called
sequence pair. All block placement algorithms which are based on sequence pairs use …

In this paper we present FAST-SP which is a fast block placement algorithm based on the
sequence-pair placement representation. FAST-SP has two significant improvements over …

We study the fixed-outline floorplan formulation that is more relevant to hierarchical design
style and is justified for very large ASICs and SOCs. We empirically show that the fixed …

The rectangle packing problem often appears in encasement and cutting as well as very
large-scale integration design. To solve this problem, many algorithms such as genetic …

Floorplanning is an important issue in the very large-scale integrated (VLSI) circuit design
automation as it determines the performance, size, yield and reliability of VLSI chips. This …

We extend in this paper the concept of the P-admissible floorplan representation to that of
the P*-admissible one. AP*-admissible representation can model the most general …

The efficiency and effectiveness of many floorplanning methods depend very much on the
representation of the geometrical relationship between the modules. A good representation …

In this paper we present a floorplanning algorithm for 3-D ICs. The problem can be
formulated as that of packing a given set of 3-D rectangular blocks while minimizing a …