Dual hydrogen barrier layer for memory devices

N Sato, N Mukherjee, M Manfrini, T Gosavi… - US Patent …, 2024 - Google Patents
A device includes, in a first region, a first conductive interconnect, an electrode structure on
the first conductive interconnect, where the electrode structure includes a first conductive …

Method of fabricating pedestal based memory devices using pocket integration

N Sato, T Gosavi, N Mukherjee, A Mathuriya… - US Patent …, 2024 - Google Patents
A pocket integration for high density memory and logic applications and methods of
fabrication are described. While various examples are described with reference to FeRAM …

Spin-orbit-torque magnetoresistive random-access memory array

D Worledge, P Hashemi, JK DeBrosse - US Patent 12,020,736, 2024 - Google Patents
A spin-orbit torque magnetoresistive random-access memory device formed by forming an
array of transistors, where a column of the array includes a source line contacting the source …

Thin film diode based back-end temperature sensors

R Pillarisetty, P Majhi, AA Sharma… - US Patent App. 15 …, 2019 - Google Patents
Electronic devices, integrated circuit device structures, and computing devices including thin
film, diode-based temperature sensors are disclosed. An electronic device includes a diode …

Pocket integration process for embedded memory

N Sato, T Gosavi, N Mukherjee, A Mathuriya… - US Patent …, 2024 - Google Patents
A pocket integration for high density memory and logic applications and methods of
fabrication are described. While various embodiments are described with reference to …

Planar and trench capacitors for logic and memory applications

SJ Rathi, N Sato, N Mukherjee… - US Patent …, 2024 - freepatentsonline.com
A device includes, in a first region, a first conductive interconnect, an electrode structure on
the first conductive interconnect, where the electrode structure includes a first conductive …

Devices with continuous electrode plate and methods of fabrication

N Sato, D Guhabiswas, T Gosavi, N Mukherjee… - US Patent …, 2024 - Google Patents
An integration process including an etch stop layer for high density memory and logic
applications and methods of fabrication are described. While various examples are …

Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications

SJ Rathi, N Sato, N Mukherjee, RK Dokania… - US Patent …, 2024 - Google Patents
A device includes, in a first region, a first conductive interconnect, an electrode structure on
the first conductive interconnect, where the electrode structure includes a first conductive …

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

SJ Rathi, N Sato, N Mukherjee, RK Dokania… - US Patent …, 2024 - Google Patents
A device includes, in a first region, a first conductive interconnect, an electrode structure on
the first conductive interconnect, where the electrode structure includes a first conductive …

Multi-level hydrogen barrier layers for memory applications

N Sato, N Mukherjee, M Manfrini, T Gosavi… - US Patent …, 2024 - Google Patents
A device includes, in a first region, a first conductive interconnect, an electrode structure on
the first conductive interconnect, where the electrode structure includes a first conductive …