A survey of architectural techniques for managing process variation

S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …

A hybrid DQN and optimization approach for strategy and resource allocation in MEC networks

YC Wu, TQ Dinh, Y Fu, C Lin… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
We consider a multi-user multi-server mobile edge computing (MEC) network with time-
varying fading channels and formulate an offloading decision and resource allocation …

Beyond DVFS: A first look at performance under a hardware-enforced power bound

B Rountree, DH Ahn, BR De Supinski… - 2012 IEEE 26th …, 2012 - ieeexplore.ieee.org
Dynamic Voltage Frequency Scaling (DVFS) has been the tool of choice for balancing
power and performance in high-performance computing (HPC). With the introduction of …

Greengpu: A holistic approach to energy efficiency in gpu-cpu heterogeneous architectures

K Ma, X Li, W Chen, C Zhang… - 2012 41st international …, 2012 - ieeexplore.ieee.org
In recent years, GPU-CPU heterogeneous architectures have been increasingly adopted in
high performance computing, because of their capabilities of providing high computational …

Scalable thread scheduling and global power management for heterogeneous many-core architectures

JA Winter, DH Albonesi, CA Shoemaker - Proceedings of the 19th …, 2010 - dl.acm.org
Future many-core microprocessors are likely to be heterogeneous, by design or due to
variability and defects. The latter type of heterogeneity is especially challenging due to its …

Towards optimal electric demand management for internet data centers

J Li, Z Li, K Ren, X Liu - IEEE Transactions on Smart Grid, 2011 - ieeexplore.ieee.org
Electricity cost is becoming a major portion of Internet data center (IDC)'s operation cost and
large-scale IDCs are becoming important consumers of regional electricity markets. IDC's …

Within-die variation-aware dynamic-voltage-frequency-scaling with optimal core allocation and thread hop** for the 80-core teraflops processor

S Dighe, SR Vangal, P Aseron, S Kumar… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
In this paper, we present measured within-die core-to-core Fmax and leakage variation data
for an 80-core processor in 65 nm CMOS and 1) populate a parameterized …

Scalable stochastic processors

S Narayanan, J Sartori, R Kumar… - … Design, Automation & …, 2010 - ieeexplore.ieee.org
Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive
scaling of voltage and frequency, and shrinking design margins. Fortunately, many …

Power tuning HPC jobs on power-constrained systems

N Gholkar, F Mueller, B Rountree - Proceedings of the 2016 International …, 2016 - dl.acm.org
As we approach the exascale era, power has become a primary bottleneck. The US
Department of Energy has set a power constraint of 20MW on each exascale machine. To …

SolarCore: Solar energy driven multi-core architecture power management

C Li, W Zhang, CB Cho, T Li - 2011 IEEE 17th international …, 2011 - ieeexplore.ieee.org
The global energy crisis and environmental concerns (eg global warming) have driven the IT
community into the green computing era. Of clean, renewable energy sources, solar power …