This paper presents an efficient solution to reduce the power consumption of the popular
linear feedback shift register by exploiting the gated clock approach. The power reduction …

The article presents a new augmented and improved MMBISR for SRAM using hybrid
redundancy analysis (HRA). The presented algorithm is the augmented version of essential …

This paper presents a hybrid memory testing approach for SRAM by clubbing two existing
conventional memory testing algorithms ie MARCH C-and Checker Board. The …

This Paper presents an exhaustive review on BIST technique used in different fault tolerant
systems and also consider the fault detection methodologies used in these systems. BIST is …

This paper describes the implementation of a shift-register based Built-In Self-Test (BIST)
architecture for FPGA global interconnection resources testing. Through this, it is possible to …

Switching activity and Transition density computation is an essential stage for dynamic
power estimation and testing time reduction. The study of switching activity, transition …

Logic BIST is a safety mechanism, which performs testing for Automotive electronics.
However, pseudorandom LBIST patterns results in increased test time and test power. In this …

This paper presents the development of a Serial Peripheral Interface (SPI) module with Built-
In Self-Test (BIST) capabilities that can accurately locate error bits during the transmission …

Designing of a reliable digital system is a challenging task because it incorporates testing of
circuits at the design time. With this feature the designer can depict testable circuit for …

Linear Feedback Shift Registers (LFSRs) represent a fundamental component in numerous
digital systems, facilitating operations ranging from sequence generation to error detection …