A survey of optimization techniques for thermal-aware 3D processors

K Cao, J Zhou, T Wei, M Chen, S Hu, K Li - Journal of Systems Architecture, 2019 - Elsevier
Interconnect scaling has become a major design challenge for traditional planar (2D)
integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers …

A survey on map** and scheduling techniques for 3D Network-on-chip

SP Kaur, M Ghose, A Pathak, R Patole - Journal of Systems Architecture, 2024 - Elsevier
Abstract Network-on-chips (NoCs) have been widely employed in the design of
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs …

Map** techniques in multicore processors: current and future trends

M Gupta, L Bhargava, S Indu - The Journal of Supercomputing, 2021 - Springer
Multicore systems are in demand due to their high performance thus making application
map** an important research area in this field. Breaking an application into multiple …

On runtime communication and thermal-aware application map** and defragmentation in 3D NoC systems

B Li, X Wang, AK Singh, T Mak - IEEE Transactions on Parallel …, 2019 - ieeexplore.ieee.org
Many-core systems connected by 3D Networks-on-Chip (NoC) are emerging as a promising
computation engine for systems like cloud computing servers, big data systems, etc …

On runtime communication-and thermal-aware application map** in 3D NoC

B Li, X Wang, AK Singh, T Mak - Proceedings of the Eleventh IEEE/ACM …, 2017 - dl.acm.org
Many-core systems connected by 3D Network-on-Chips (NoC) are emerging as a promising
computation engine for systems like cloud computing servers, big data systems, etc …

Int-TAR: An intelligent thermal-aware routing algorithm for 3D NoC

Z Shirmohammadi, M Mahmoudi… - Journal of Electrical …, 2022 - jecei.sru.ac.ir
Background and Objectives: Thermal problem is one of the main challenges in 3D on-chip
networks. Inappropriate traffic distribution, poor heat dissipation, cooling restriction for layers …

Augmented cross-entropy-based joint temperature optimization of real-time 3-D MPSoC systems

Y Cui, K Cao, L Li, J Zhou, T Wei… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
3-D multiprocessor system-on-chip (MPSoC) systems can offer higher integration density,
lower interaction cost, better bandwidth, and greater performance. However, vertically …

Yield-aware joint die packing, die matching and static thread map** for hard real-time 3D embedded CMPs

A Siavashi, M Momtazpour - Microprocessors and Microsystems, 2022 - Elsevier
This paper addresses the problem of performance and thermal yield maximization for hard
real-time 3D embedded chip multiprocessors. We propose a process variation-aware …

The Thermal-Constrained Real-Time Systems Design on Multi-Core Platforms--An Analytical Approach

SHI SHA - 2018 - digitalcommons.fiu.edu
Over the past decades, the shrinking transistor size enabled more transistors to be
integrated into an IC chip, to achieve higher and higher computing performances. However …