Recent trends on junction-less field effect transistors in terms of device topology, modeling, and application
Junction less field effect transistor, also known as JLFET, is widely regarded as the most
promising candidate that has the potential to replace the more conventional MOSFET used …
promising candidate that has the potential to replace the more conventional MOSFET used …
A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications
This article critically reviews the fabrication challenges, emerging materials (wafer, high-k
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …
Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes
In this paper, for the first time, we have investigated the DC, analog/RF, and linearity metrics
of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire …
of asymmetric spacer junctionless (JL) Gate-All-Around (GAA) vertically stacked nanowire …
Performance evaluation of GAA nanosheet FET with varied geometrical and process parameters
NA Kumari, P Prithvi - Silicon, 2022 - Springer
Abstract Nanosheet Field Effect Transistor (NSFET) is a viable contender for future scaling in
sub-7-nm technology. This paper provides insights into the variations of DC FOMs for …
sub-7-nm technology. This paper provides insights into the variations of DC FOMs for …
Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications
Multi‐fin devices are the most reliable option for terahertz (THz) frequency applications at
nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is …
nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is …
Optimizing u-shape FinFETs for sub-5nm technology: performance analysis and device-to-circuit evaluation in digital and analog/radio frequency applications
FinFET is considered as the potential contender in the era of Multigate FETs. This
manuscript for the first time presents the structural variations for Junctionless FinFET devices …
manuscript for the first time presents the structural variations for Junctionless FinFET devices …
A comprehensive analysis and performance comparison of CombFET and NSFET for CMOS circuit applications
NA Kumari, P Prithvi - AEU-International Journal of Electronics and …, 2023 - Elsevier
The performance of comb-like channel field effect transistor (CombFET) and nanosheet FET
(NSFET) is addressed at both device and circuit levels at the 3-nm node. The CombFET is …
(NSFET) is addressed at both device and circuit levels at the 3-nm node. The CombFET is …
A study of an ultrasensitive label free silicon nanowire FET biosensor for cardiac troponin I detection
This study evolves an ultrasensitive label free electrical device, the silicon nanowire field
effect transistor (SiNW FET) for cardiac troponin I (cTnI) in acute myocardial infarction (AMI) …
effect transistor (SiNW FET) for cardiac troponin I (cTnI) in acute myocardial infarction (AMI) …
Junctionless gate-all-around nanowire FET with asymmetric spacer for continued scaling
In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire
(NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC …
(NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC …
Circuit analysis and optimization of GAA nanowire FET towards low power and high switching
The main aim of this work is to study the effect of symmetric and asymmetric spacer length
variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire …
variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire …