[PDF][PDF] Intel SGX explained

V Costan - IACR Cryptol, EPrint Arch, 2016 - people.cs.rutgers.edu
Abstract Intel's Software Guard Extensions (SGX) is a set of extensions to the Intel
architecture that aims to provide integrity and privacy guarantees to security-sensitive …

Modified decode for corner turn

G Kirsch, M Steadman - US Patent 9,899,070, 2018 - Google Patents
Examples of the present disclosure provide apparatuses and methods for performing a
corner turn using a modified decode. An example apparatus can comprise an array of …

Secure processors part I: background, taxonomy for secure enclaves and Intel SGX architecture

V Costan, I Lebedev, S Devadas - Foundations and Trends® …, 2017 - nowpublishers.com
This manuscript is the first in a two part survey and analysis of the state of the art in secure
processor systems, with a specific focus on remote software attestation and software …

Apparatuses and methods for performing corner turn operations using sensing circuitry

JT Zawodny, S Tiwari - US Patent 10,153,008, 2018 - Google Patents
The present disclosure includes apparatuses and methods related to performing corner turn
operations using sensing circuitry. An example apparatus comprises a first group of memory …

Coalescing adjacent gather/scatter operations

AT Forsyth, BJ Hickmann, JC Hall… - US Patent 9,348,601, 2016 - Google Patents
According to one embodiment, a processor includes an instruction decoder to decode a first
instruction to gather data elements from memory, the first instruction having a first operand …

Method and apparatus for performing reduction operations on a set of vector elements

DM Kunzman, CJ Hughes - US Patent 9,851,970, 2017 - Google Patents
An apparatus and method are described for performing SIMD reduction operations. For
example, one embodiment of a processor comprises: a value vector register containing a …

No-locality hint vector memory access processors, methods, systems, and instructions

CJ Hughes - US Patent 9,600,442, 2017 - Google Patents
(57) ABSTRACT A processor of an aspect includes a plurality of packed data registers, and
a decode unit to decode a no-locality hint vector memory access instruction. The no-locality …

Gather using index array and finite state machine

Z Sperber, R Valentine, G Patkin… - US Patent …, 2015 - Google Patents
2012-07-13 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …

Scatter using index array and finite state machine

Z Sperber, R Valentine, S Raikin… - US Patent …, 2017 - Google Patents
Methods and apparatus are disclosed using an index array and finite state machine for
scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode …

Instructions for storing in general purpose registers one of two scalar constants based on the contents of vector write masks

J Corbal, MJ Craighead, BL Toll, AT Forsyth - US Patent 10,157,061, 2018 - Google Patents
According to one embodiment, an occurrence of an instruction is fetched. The instruction's
format specifies its only source operand from a single vector write mask register, and …