Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates
The current use of multi-Vt to control leakage power targets combinational gates, even
though sequential elements such as flip-flops and latches also contribute appreciable …
though sequential elements such as flip-flops and latches also contribute appreciable …
Dual-Vth leakage reduction with fast clock skew scheduling enhancement
M Tie, H Dong, T Wang, X Cheng - 2010 Design, Automation & …, 2010 - ieeexplore.ieee.org
Dual-Vth technique is a mature and effective method for reducing leakage power
consumption. Previously proposed algorithms assign logic gates with sufficient timing slack …
consumption. Previously proposed algorithms assign logic gates with sufficient timing slack …
PMD: A low-power code for networks-on-chip based on virtual channels
Virtual channels are a common alternative for providing quality-of-service to Networks-on-
Chip. A drawback of the approach is the increased power consumption because of the …
Chip. A drawback of the approach is the increased power consumption because of the …
A New Low Leakage Power Flip-Flop Based on Ratioed Latches with Power Gating
X Yu, J Hu - Procedia Environmental Sciences, 2011 - Elsevier
This paper presents a new low leakage power flip-flop based on CMOS ratioed latches with
the master-slave structure. Dual-threshold CMOS (DTCMOS) and channel length biasing …
the master-slave structure. Dual-threshold CMOS (DTCMOS) and channel length biasing …
The performance and behaviour of dual edge triggered flip-flops in nanotechnology
A Rjoub, MM Al-Durrah - International Journal of Computer …, 2012 - inderscienceonline.com
The influence of the nanotechnology on the most frequent used dual edge trigger flip-flops
(DET-FF) is presented in this paper. The performance and behavioural of those flip-flops are …
(DET-FF) is presented in this paper. The performance and behavioural of those flip-flops are …