Research progress on memristor: From synapses to computing systems
As the limits of transistor technology are approached, feature size in integrated circuit
transistors has been reduced very near to the minimum physically-realizable channel length …
transistors has been reduced very near to the minimum physically-realizable channel length …
[HTML][HTML] Toolflow for the algorithm-hardware co-design of memristive ANN accelerators
The capabilities of artificial neural networks are rapidly evolving, so are the expectations for
them to solve ever more challenging tasks in numerous everyday situations. Larger, more …
them to solve ever more challenging tasks in numerous everyday situations. Larger, more …
Architecting decentralization and customizability in dnn accelerators for hardware defect adaptation
The efficiency of machine intelligence techniques has improved noticeably in the embedded
application domains thanks to the dedicated hardware accelerators for deep neural …
application domains thanks to the dedicated hardware accelerators for deep neural …
TEFLON: Thermally Efficient Dataflow-Aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures
Resistive random-access memory (ReRAM)-based processing-in-memory (PIM)
architectures are used extensively to accelerate inferencing/training with convolutional …
architectures are used extensively to accelerate inferencing/training with convolutional …
Hybrid RRAM/SRAM in-memory computing for robust DNN acceleration
RRAM-based in-memory computing (IMC) effectively accelerates deep neural networks
(DNNs) and other machine learning algorithms. On the other hand, in the presence of RRAM …
(DNNs) and other machine learning algorithms. On the other hand, in the presence of RRAM …
Approximate computing and the efficient machine learning expedition
Approximate computing (AxC) has been long accepted as a design alternative for efficient
system implementation at the cost of relaxed accuracy requirements. Despite the AxC …
system implementation at the cost of relaxed accuracy requirements. Despite the AxC …
Essence: Exploiting structured stochastic gradient pruning for endurance-aware reram-based in-memory training systems
Processing-in-memory (PIM) enables energy-efficient deployment of convolutional neural
networks (CNNs) from edge to cloud. Resistive random-access memory (ReRAM) is one of …
networks (CNNs) from edge to cloud. Resistive random-access memory (ReRAM) is one of …
Harmonica: Hybrid Accelerator to Overcome Imperfections of Mixed-signal DNN Accelerators
In recent years, PIM-based mixed-signal accelerators have been proposed as energy-and
area-efficient solutions with ultra-high throughput to accelerate DNN computations …
area-efficient solutions with ultra-high throughput to accelerate DNN computations …
Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design
The rapid progress of artificial intelligence (AI) has led to the emergence of a highly
promising field known as neuro-symbolic (NeSy) computing. This approach combines the …
promising field known as neuro-symbolic (NeSy) computing. This approach combines the …
TransCODE: Co-design of transformers and accelerators for efficient training and inference
Automated co-design of machine learning models and evaluation hardware is critical for
efficiently deploying such models at scale. Despite the state-of-the-art performance of …
efficiently deploying such models at scale. Despite the state-of-the-art performance of …