Challenges and Trends in Modern SoC Design Verification Page 1 7 2168-2356/17 © 2017
IEEE Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC September/October …

Functional coverage is a de facto standard for monitoring the state of the verification process
and its progress. Therefore, coverage closure, which is the process of advancing coverage …

Modern hardware functional verification employs many different tools alongside large
compute farms to ensure that the hardware's implementation matches its specification. This …

Identifying large and important coverage holes is a time-consuming process that requires
expertise in the design and its verification environment. This paper describes a novel …

Understanding the relationship between coverage and test-templates (a generic term we
use to describe the inputs for the random stimuli generator) is an important layer in …

A method, apparatus and product for reducing a number of test templates in a test suite. The
method comprises determining, for a first test template of the test suite, a first probabilities …

Verification in general and specifically functional verification are, without a doubt, some of
the most important and labor-intensive parts of a hardware design cycle. Some market …

Early identification of areas that are at-risk in a design under development can help design
and verification teams take early preventive and corrective measures. We propose a novel …

Due to the complexity of designs, post-silicon validation remains a major challenge with few
systematic solutions. We provide an overview of the state-of-the-art post silicon validation …