Due to the constant scaling of device sizes and the arrival of nanoscale technologies, Single-
Event Transients (SETs) are becoming an increasingly important problem in the design and …

The exponential dependence of the soft error rate (SER) with critical charge in CMOS
circuits, empirically proposed by Hazucha and Svensson, is derived in the framework of the …

This paper studies the Soft Error Rates (SER) of latches by using different delay lengths in
guard-gate based Flip-Flop (FF) designs at a 12-nm FinFET technology node. Three FFs are …

Area efficient self-correcting flip-flops for use with triple modular redundant (TMR) soft-error
hardened logic are implemented in a 12-nm finFET process technology. The TMR flip-flop …

Many aerospace users of radiation hardened (RH) components have radiation performance
requirements that are relatively minor compared to traditional RH requirements. By relaxing …

As the geometries of transistors continue to scale down, single-event transient (SET) are
becoming a major source of soft errors in circuit design. This paper proposes a machine …

CMOS technologies continue to evolve with the promise of improved computation,
integration and power performances, while the diffusion of off-the-shelf components into …

A simple simulation-based approach to accurately estimating the single even effect (SEE)
cross section of a standard cell library Flip-Flop is presented. A SPICE level model of charge …