Cu gap-fill is enhanced by replacing the conventional Ta liner with a Co liner in a 22 nm
width interconnect structure. The improvement with Co liner seen at the line-end area is …

Abstract Through Silicon Via (TSV) technology is essential to accomplish 3-dimensional
packaging of electronics. Hence, more reliable and faster TSV filling by Cu electrodeposition …

High aspect ratio through Si vias (φ 2μm, depth 30μm) have been filled completely by Cu
electroplating using an electroless deposited Cu seed layer. The electroless Cu deposition …

For the analysis of thin films, with high aspect ratio (HAR) structures, time-of-flight secondary
ion mass spectrometry (ToF-SIMS) overcomes several challenges in comparison to other …

With the reduction of the feature of GLSI, cobalt (Co) became a novel barrier material due to
its low resistivity and adhesion ability. On account of the different physical and chemical …

The chemically synthesized suppressor and leveler are added together with bis (3-
sulfopropyl) disulfide (SPS) to galvanostatically fill up the trenches with the similar …

Bath stability monitoring of electroless copper deposition has been done with different
methods. A combination of UV-VIS spectra and pH measurement enabled us to determine …

Through-silicon vias (TSV) will speed up interconnections between chips. Manufacturable
and cost-effective TSVs will allow faster computer systems. In this paper, we report the …

An alkaline, tartrate-complexed copper electrolyte containing additives that provide bottom-
up fill is described. Bottom-up fill is achieved using a mixture of two additives: bis-(3 …

Higher performance, higher operation speed and volume shrinkage require high 3D
interconnect densities. A way to meet the density specifications is to further increase the AR …