Time-to-digital converters (TDCs) are high-performance mixed-signal circuits capable of
timestam** events with sub-gate delay resolution. As a result of their high-performance, in …

In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate,
and programmable gain for a wide input range. Using the proposed pulse-train time …

This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …

We present a novel architecture for multi-channel time-to-digital converters (TDCs) to be
implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least …

This paper describes a reference-clock-free, high-time-resolution on-chip timing jitter
measurement circuit using a self-referenced clock and a cascaded time difference amplifier …

This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter
(TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline …

This paper presents an 8-bit 1.25-ps resolution reconfigurable Vernier time-to-digital
converter (TDC) with a 2-D spiral comparator array and ΔΣ modulators for linearization. The …

A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of
delay latches is proposed. The delay latches replace the functionality of one delay chain and …

In this paper, a Nyquist ADC with a time-based pipelined TDC is proposed. In the proposed
ADC, the first pipeline stage incorporates both residue amplification and a VT conversion …

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave
Union type A (WU-A) architecture for applications that require high-precision time interval …