Past research has proposed numerous hardware prefetching techniques, most of which rely
on exploiting one specific type of program context information (eg, program counter …

Recent years have seen a dramatic increase in the microarchitectural complexity of
processors. This increase in complexity presents a twofold challenge for the field of …

We present Decoupled Vector Runahead (DVR), an in-core prefetching technique,
executing separately to the main application thread, that exploits massive amounts of …

Research into processor-based side-channels has seen both a large number and a large
variety of disclosed vulnerabilities that can leak critical, private data to malicious attackers …

Long-latency load requests continue to limit the performance of modern high-performance
processors. To increase the latency tolerance of a processor, architects have primarily relied …

Hardware prefetching is a latency-hiding technique that hides the costly off-chip DRAM
accesses. However, state-of-the-art prefetchers fail to deliver performance improvement in …

The past decade has seen the rise of highly successful cache replacement policies that are
based on binary prediction. For example, the Hawkeye policy learns whether lines loaded …

Online Reinforcement Learning (RL) has been adopted as an effective mechanism in
various decision-making problems in microarchitecture. Its high adaptability and the ability to …

Data prefetching is a technique that plays a crucial role in modern high-performance
processors by hiding long latency memory accesses. Several state-of-the-art hardware …

Graphics Processing Units (GPUs) utilize memory hierarchy and Thread-Level Parallelism
(TLP) to tolerate off-chip memory latency, which is a significant bottleneck for memory-bound …