VARIUS: A model of process variation and resulting timing errors for microarchitects

SR Sarangi, B Greskamp, R Teodorescu… - IEEE Transactions …, 2008 - ieeexplore.ieee.org
Within-die parameter variation poses a major challenge to high-performance
microprocessor design, negatively impacting a processor's frequency and leakage power …

Statistical timing analysis: From basic principles to state of the art

D Blaauw, K Chopra, A Srivastava… - IEEE transactions on …, 2008 - ieeexplore.ieee.org
Static-timing analysis (STA) has been one of the most pervasive and successful analysis
engines in the design of digital circuits for the last 20 years. However, in recent years, the …

A Bayesian joint probability modeling approach for seasonal forecasting of streamflows at multiple sites

QJ Wang, DE Robertson… - Water Resources …, 2009 - Wiley Online Library
Seasonal forecasting of streamflows can be highly valuable for water resources
management. In this paper, a Bayesian joint probability (BJP) modeling approach for …

Common-centroid layout for active and passive devices: A review and the road ahead

N Karmokar, M Madhusudan… - 2022 27th Asia and …, 2022 - ieeexplore.ieee.org
This paper presents an overview of common-centroid (CC) layout styles, used in analog
designs to overcome the impact of systematic variations. CC layouts must be carefully …

Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors

B Raghunathan, Y Turakhia, S Garg… - … Design, Automation & …, 2013 - ieeexplore.ieee.org
It is projected that increasing on-chip integration with technology scaling will lead to the so-
called dark silicon era in which more transistors are available on a chip than can be …

Statistical training for neuromorphic computing using memristor-based crossbars considering process variations and noise

Y Zhu, GL Zhang, T Wang, B Li, Y Shi… - … , Automation & Test …, 2020 - ieeexplore.ieee.org
Memristor-based crossbars are an attractive platform to accelerate neuromorphic computing.
However, process variations during manufacturing and noise in memristors cause significant …

ReCycle: Pipeline adaptation to tolerate process variation

A Tiwari, SR Sarangi, J Torrellas - ACM SIGARCH Computer Architecture …, 2007 - dl.acm.org
Process variation affects processor pipelines by making some stages slower and others
faster, therefore exacerbating pipeline unbalance. This reduces the frequency attainable by …

Common-centroid layouts for analog circuits: Advantages and limitations

AK Sharma, M Madhusudan, SM Burns… - … , Automation & Test …, 2021 - ieeexplore.ieee.org
Common-centroid (CC) layouts are widely used in analog design to make circuits resilient to
variations by matching device characteristics. However, CC layout may involve increased …

Hayat: Harnessing dark silicon and variability for aging deceleration and balancing

D Gnad, M Shafique, F Kriebel, S Rehman… - Proceedings of the …, 2015 - dl.acm.org
Elevated power densities result in the so-called Dark Silicon constraint that prohibits
simultaneous activation of all the cores in an on-chip system (in the full performance mode) …

[CARTE][B] Advanced field-solver techniques for RC extraction of integrated circuits

W Yu, X Wang - 2014 - Springer
The main goal of writing this book was to present a methodological and algorithmic
perspective on the field-solver-based parasitic extraction of integrated circuits (ICs) …