This paper reviews several full adder (FA) designs in single-electron technology (SET). In
addition to the structure and size (ie, number of devices), this paper tries to provide a …

Motivated by the need for economical fault-tolerant designs for nanoarchitectures, we
explore a novel multiplexing-based redundant design scheme at small (/spl les/100) and …

This book is intended to give a general overview of reliability, faults, fault models,
nanotechnology, nanodevices, fault-tolerant architectures and reliability evaluation …

This paper studies the reliability of three different majority gates full adder (FA) designs, and
compares them with that of a standard XOR-based FA. The analysis provides insights into …

This work presents a novel architecture, which is both device and circuit independent. The
starting idea is that computations can be performed in three fundamentally different ways …

Motivated by the need for cost-effective fault-tolerant nano architectures, we explore von
Neumann multiplexing (vN-MUX) at small and very small redundancy factors. We present a …

In this paper we have proposed a new and more accurate macro-model for simulation of
single electron transistors (SETs). Furthermore, this model includes the ability of electron …

This chapter will start with a brief review of nanoelectronic challenges while focusing on the
reliability challenge. One of the most recent call-to-arms [1] raises two fundamental …

This paper will briefly review nanoelectronic challenges while focusing on reliability. We
shall present and analyze a series of CMOS-based examples for addition starting from the …

As one of the most promising candidates for future digital circuit applications, single-electron
tunneling (SET) technology has been used to ensure further feature size reduction and …