All-digital PLL and transmitter for mobile phones
RB Staszewski, JL Wallberg, S Rezeq… - IEEE journal of Solid …, 2005 - ieeexplore.ieee.org
We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a
single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The …
single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The …
Clocking analysis, implementation and measurement techniques for high-speed data links—A tutorial
The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …
precision of their clocking infrastructure. For future applications, such as microprocessor …
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
RB Staszewski, S Vemulapalli, P Vallur… - … on Circuits and …, 2006 - ieeexplore.ieee.org
We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm
digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an …
digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an …
A Low-Noise Wide-BW 3.6-GHz Digital Fractional-N Frequency Synthesizer With a Noise-Sha** Time-to-Digital Converter and Quantization Noise Cancellation
A 3.6-GHz digital fractional-N frequency synthesizer achieving low noise and 500-kHz
bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital …
bandwidth is presented. This architecture uses a gated-ring-oscillator time-to-digital …
An efficient mixed-signal 2.4-GHz polar power amplifier in 65-nm CMOS technology
A 65-nm digitally modulated polar transmitter incorporates a fully integrated, efficient 2.4-
GHz switching Inverse Class-D power amplifier. Low-power digital filtering on the amplitude …
GHz switching Inverse Class-D power amplifier. Low-power digital filtering on the amplitude …
A fully integrated 24-GHz phased-array transmitter in CMOS
This paper presents the first fully integrated 24-GHz phased-array transmitter designed
using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS …
using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS …
A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones
We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular
mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver …
mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver …
A DTC-based subsampling PLL capable of self-calibrated fractional synthesis and two-point modulation
We present an analog subsampling PLL based on a digital-to-time converter (DTC), which
operates with almost no performance gap (176/198 fs RMS jitter) between the integer and …
operates with almost no performance gap (176/198 fs RMS jitter) between the integer and …
Design of CMOS power amplifiers
This paper describes the key technology and circuit design issues facing the design of an
efficient linear RF CMOS power amplifier for modern communication standards …
efficient linear RF CMOS power amplifier for modern communication standards …
A digital PLL with a stochastic time-to-digital converter
V Kratyuk, PK Hanumolu, K Ok… - … on Circuits and …, 2008 - ieeexplore.ieee.org
A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a
stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to …
stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to …