Advances in logic locking: Past, present, and prospects

HM Kamali, KZ Azar, F Farahmandi… - Cryptology ePrint …, 2022 - eprint.iacr.org
Logic locking is a design concealment mechanism for protecting the IPs integrated into
modern System-on-Chip (SoC) architectures from a wide range of hardware security threats …

Progress and challenges in VLSI placement research

IL Markov, J Hu, MC Kim - … of the International Conference on Computer …, 2012 - dl.acm.org
Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

AutoBridge: Coupling coarse-grained floorplanning and pipelining for high-frequency HLS design on multi-die FPGAs

L Guo, Y Chi, J Wang, J Lau, W Qiao, E Ustun… - The 2021 ACM/SIGDA …, 2021 - dl.acm.org
Despite an increasing adoption of high-level synthesis (HLS) for its design productivity
advantages, there remains a significant gap in the achievable clock frequency between an …

Machine learning in advanced IC design: A methodological survey

T Chen, GL Zhang, B Yu, B Li… - IEEE Design & …, 2022 - ieeexplore.ieee.org
The increasing complexity and size of design space poses significant challenges for
integrated circuit (IC) design. This article discusses the potential of machine learning (ML) …

Eco-chip: Estimation of carbon footprint of chiplet-based architectures for sustainable vlsi

CC Sudarshan, N Matkar, S Vrudhula… - … Symposium on High …, 2024 - ieeexplore.ieee.org
Decades of progress in energy-efficient and low-power design have successfully reduced
the operational carbon footprint in the semiconductor industry. However, this has led to …

LAYGEN II—Automatic layout generation of analog integrated circuits

R Martins, N Lourenco, N Horta - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
This paper describes an innovative design automation tool, LAYGEN II, for analog integrated
circuit (IC) layout generation based on template descriptions and on evolutionary …

A SimPLR method for routability-driven placement

MC Kim, J Hu, DJ Lee, IL Markov - 2011 IEEE/ACM …, 2011 - ieeexplore.ieee.org
Highly-optimized placements may lead to irreparable routing congestion due to inadequate
models of modern interconnect stacks and the impact of partial routing obstacles. Additional …

Progress of placement optimization for accelerating VLSI physical design

Y Qiu, Y **ng, X Zheng, P Gao, S Cai, X **ong - Electronics, 2023 - mdpi.com
Placement is essential in very large-scale integration (VLSI) physical design, as it directly
affects the design cycle. Despite extensive prior research on placement, achieving fast and …

Customized retrieval augmented generation and benchmarking for eda tool documentation qa

Y Pu, Z He, T Qiu, H Wu, B Yu - arxiv preprint arxiv:2407.15353, 2024 - arxiv.org
Retrieval augmented generation (RAG) enhances the accuracy and reliability of generative
AI models by sourcing factual information from external databases, which is extensively …

[BUCH][B] Graphs in VLSI

R Bairamkulov, EG Friedman - 2023 - Springer
Advances in semiconductor fabrication technology have produced explosive growth in the
number of transistors within an integrated circuit (IC). Modern devices consist of dozens of …