Recent trends in deep learning (DL) imposed hardware accelerators as the most viable
solution for several classes of high-performance computing (HPC) applications such as …

ESP is an open-source research platform for heterogeneous SoC design. The platform
combines a modular tile-based architecture with a variety of application-oriented flows for …

We present the nanoPU, a new NIC-CPU co-design to accelerate an increasingly pervasive
class of datacenter applications: those that utilize many small Remote Procedure Calls …

Data-parallel problems demand ever growing floating-point (FP) operations per second
under tight area-and energy-efficiency constraints. In this work, we present Manticore, a …

Modern computing systems employ significant heterogeneity and specialization to meet
performance targets at manageable power. However, memory latency bottlenecks remain …

Heterogeneous architectures and heterogeneous-ISA designs are growing areas of
computer architecture and system software research. Unfortunately, this line of research is …

Applications with low data reuse and frequent irregular memory accesses, such as graph or
sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core …

On-chip communication infrastructure is a central component of modern systems-on-chip
(SoCs), and it continues to gain importance as the number of cores, the heterogeneity of …

The design space exploration of scaled-out manycores for communication-intensive
applications (eg, graph analytics and sparse linear algebra) is hampered due to either lack …

Convolution neural networks (CNNs) have demonstrated superior capability in computer
vision, speech recognition, autonomous driving, and so forth, which are opening up an …