Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design
Automation (EDA) has been able to cope with the challenging very large-scale integration …

The integration of a complex set of Electronic Design Automation (EDA) tools to enhance
interoperability is a critical concern for circuit designers. Recent advancements in large …

With the rapid development of deep learning applications, general-purpose processors no
longer suffice for deep learning workloads because of the dying of Moore's Law. Thus …

Computational lithography provides algorithmic and mathematical support for resolution
enhancement in optical lithography, which is the critical step in semiconductor …

As one of the key techniques for resolution enhancement technologies (RETs), optical
proximity correction (OPC) suffers from prohibitive computational costs as feature sizes …

Coarse-grained reconfigurable arrays (CGRAs), loosely defined as arrays of functional units
interconnected through a network-on-chip (NoC), provide higher flexibility than domain …

Presently with technology node scaling, an accurate prediction model at early design stages
can significantly reduce the design cycle. Especially during logic synthesis, predicting cell …

Pre-routing timing prediction has been recently studied for evaluating the quality of a
candidate cell placement in chip design. It involves directly estimating the timing metrics for …

Placement is central to IC physical design: it determines spatial embedding, and hence
parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized …

Logic synthesis is a challenging and widely-researched combinatorial optimization problem
during integrated circuit (IC) design. It transforms a high-level description of hardware in a …