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Space efficient sequence alignment for sram-based computing: X-drop on the graphcore IPU
Dedicated accelerator hardware has become essential for processing AI-based workloads,
leading to the rise of novel accelerator architectures. Furthermore, fundamental differences …
leading to the rise of novel accelerator architectures. Furthermore, fundamental differences …
Massive data-centric parallelism in the chiplet era
Recent works have introduced task-based parallelization schemes to accelerate graph
search and sparse data-structure traversal, where some solutions scale up to thousands of …
search and sparse data-structure traversal, where some solutions scale up to thousands of …
Exploiting deep learning accelerators for neuromorphic workloads
Spiking neural networks (SNNs) have achieved orders of magnitude improvement in terms
of energy consumption and latency when performing inference with deep learning …
of energy consumption and latency when performing inference with deep learning …
Intelligence processing units accelerate neuromorphic learning
Spiking neural networks (SNNs) have achieved orders of magnitude improvement in terms
of energy consumption and latency when performing inference with deep learning …
of energy consumption and latency when performing inference with deep learning …
Performance Evaluation of Parallel Graphs Algorithms Utilizing Graphcore IPU
Recent years have been characterized by increasing interest in graph computations. This
trend can be related to the large number of potential application areas. Moreover, increasing …
trend can be related to the large number of potential application areas. Moreover, increasing …
ipug for multiple graphcore ipus: Optimizing performance and scalability of parallel breadth-first search
Parallel graph algorithms have become one of the principal applications of high-
performance computing besides numerical simulations and machine learning workloads …
performance computing besides numerical simulations and machine learning workloads …
Steering customized ai architectures for hpc scientific applications
AI hardware technologies have revolutionized computational science. While they have been
mostly used to accelerate deep learning training and inference models for machine learning …
mostly used to accelerate deep learning training and inference models for machine learning …
Tascade: Hardware support for atomic-free, asynchronous and efficient reduction trees
Graph search and sparse data-structure traversal workloads contain challenging irregular
memory patterns on global data structures that need to be modified atomically. Distributed …
memory patterns on global data structures that need to be modified atomically. Distributed …
Implementing spatio-temporal graph convolutional networks on graphcore ipus
J Moe, K Pogorelov, DT Schroeder… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
Artificial neural networks have been used for a multitude of regression tasks, and their
descendants have expanded the domain to many applications such as image and speech …
descendants have expanded the domain to many applications such as image and speech …
Enabling unstructured-mesh computation on massively tiled AI processors: An example of accelerating in silico cardiac simulation
A new trend in processor architecture design is the packaging of thousands of small
processor cores into a single device, where there is no device-level shared memory but …
processor cores into a single device, where there is no device-level shared memory but …