3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being
increasingly dominated by the interconnects due to decreasing wire pitch and increasing die …
increasingly dominated by the interconnects due to decreasing wire pitch and increasing die …
Activated chemical process for enhancing material properties of dielectric films
(57) ABSTRACT A method for restoring a dielectric constant of a layer of a silicon-containing
dielectric material having a first dielectric constant and at least one Surface, wherein the first …
dielectric material having a first dielectric constant and at least one Surface, wherein the first …
Multiple Si layer ICs: Motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing
interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that …
interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that …
High-performance interconnects: An integration overview
RH Havemann, JA Hutchby - Proceedings of the IEEE, 2001 - ieeexplore.ieee.org
The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI)
have spawned an ever-increasing level of functional integration on-chip, driving a need for …
have spawned an ever-increasing level of functional integration on-chip, driving a need for …
[كتاب][B] Interconnect Performance in 3-Dimensional Integrated Circuits
SJ Souri - 2003 - search.proquest.com
The speed of deep submicron very large scale integrated circuits is being increasingly
dominated by interconnects due to decreasing wire pitch, increasing circuit complexity and …
dominated by interconnects due to decreasing wire pitch, increasing circuit complexity and …
[PDF][PDF] Getting to the bottom of deep submicron
The magnitude of the difficukies associated with the plunge of circuit design into deep
subrnicron@ Sh~ process geometries has been the source of much speculation. One …
subrnicron@ Sh~ process geometries has been the source of much speculation. One …
Tunneling-based SRAM
JPA van der Wagt - Proceedings of the IEEE, 1999 - ieeexplore.ieee.org
This paper describes a new high-density low-power circuit approach for implementing static
random access memory (SRAM) using low current density resonant tunneling diodes …
random access memory (SRAM) using low current density resonant tunneling diodes …
Analytical modeling and characterization of deep-submicrometer interconnect
This work addresses two fundamental concepts regarding deep-submicrometer
interconnect. First, characterization of on-chip interconnect is considered with particular …
interconnect. First, characterization of on-chip interconnect is considered with particular …
Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects
Presents both compact analytical models and fast SPICE based 3-D electro-thermal
simulation methodology to characterize thermal effects due to Joule heating in high …
simulation methodology to characterize thermal effects due to Joule heating in high …
Thermal stress characteristics of Cu/oxide and Cu/low-k submicron interconnect structures
Thermal stress characteristics of single damascene Cu lines passivated with tetraethyl
orthosilicate oxide and methyl silsesquioxane low-k dielectrics were investigated by x-ray …
orthosilicate oxide and methyl silsesquioxane low-k dielectrics were investigated by x-ray …