VR-ZYCAP: a versatile resourse-level ICAP controller for ZYNQ SOC
Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for
example, **linx ZynQ SoC—are increasingly being used as a single-chip solution in several …
example, **linx ZynQ SoC—are increasingly being used as a single-chip solution in several …
A fully parameterized virtual coarse grained reconfigurable array for high performance computing applications
Field Programmable Gate Arrays (FPGAs) have proven their potential in accelerating High
Performance Computing (HPC) Applications. Conventionally such accelerators …
Performance Computing (HPC) Applications. Conventionally such accelerators …
How to efficiently reconfigure tunable lookup tables for dynamic circuit specialization
Dynamic Circuit Specialization is used to optimize the implementation of a parameterized
application on an FPGA. Instead of implementing the parameters as regular inputs, in the …
application on an FPGA. Instead of implementing the parameters as regular inputs, in the …
An integrated approach and tool support for the design of fpga-based multi-grain reconfigurable systems
Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as
large as the whole reconfigurable fabric or as small as individual logic elements. However …
large as the whole reconfigurable fabric or as small as individual logic elements. However …
MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization
Abstract Dynamic Circuit Specialization (DCS) is used to optimize parts of an application
and switch between the specialized parts utilizing Partial Reconfiguration at the run-time …
and switch between the specialized parts utilizing Partial Reconfiguration at the run-time …
EPOCH: Enabling Preemption Operation for Context Saving in Heterogeneous FPGA Systems
FPGAs are increasingly used in multi-tenant cloud environments to offload compute-
intensive tasks from the main CPU. The operating system (OS) plays a vital role in identifying …
intensive tasks from the main CPU. The operating system (OS) plays a vital role in identifying …
In-circuit fault tolerance for FPGAs using dynamic reconfiguration and virtual overlays
Reassuring fault tolerance in computing systems is an important problem in high-reliability
applications. With the interest in commercial SRAM-based FPGAs in radiation environments …
applications. With the interest in commercial SRAM-based FPGAs in radiation environments …
Power measurements and analysis for dynamic circuit specialization
A Kulkarni, R Bonamy… - … Computing and FPGAs …, 2015 - ieeexplore.ieee.org
Dynamic Circuit Specialization (DCS) is a technique for optimized FPGA implementation
and is built on top of Partial Reconfiguration (PR). Dynamic Partial Reconfiguration (DPR) …
and is built on top of Partial Reconfiguration (PR). Dynamic Partial Reconfiguration (DPR) …
A 16-bit reconfigurable encryption processor for p-cipher
This paper presents an improved hardware implementation of a 16-bit ARX (Add, Rotate,
and Xor) engine for one of the CAESAR second-round competition candidates, Pi-Cipher …
and Xor) engine for one of the CAESAR second-round competition candidates, Pi-Cipher …
Partial dynamic reconfiguration framework for FPGA: A survey with concepts, constraints and trends
With demand for high performance and huge logic dense portable devices, the need for
silicon area is increasing. A potential solution for the electronics industry to develop such …
silicon area is increasing. A potential solution for the electronics industry to develop such …