A high performance, race eliminated, two phase nonoverlap** clocked All-N-Logic for both strong and subthreshold designs
M Kargar… - The 16th CSI International …, 2012 - ieeexplore.ieee.org
In this paper, a new structure of ANL logic, named TPANL, is presented to achieve higher
performance, lower power consumption and eliminating glitches. Different ANL logics suffer …
performance, lower power consumption and eliminating glitches. Different ANL logics suffer …
[PDF][PDF] Exploiting Design Of Synchronous Counters Method To Design And Implement Mod 6 Direct Down Counter
In this paper, the design of direct mod 6 down counter is proposed by using JK Flip Flop. The
counter is provided with synchronous clock pulse. The counter is implemented by using …
counter is provided with synchronous clock pulse. The counter is implemented by using …
[PDF][PDF] PROFICIENT REALIZATION OF ENHANCED BOOTH MULTIPLIER FOR SIGNED AND UNSIGNED BITS
Multipliers play vital role in most of the high performance systems. Performance of a system
depends mostly on the performance of multiplier thus multipliers should be fast and …
depends mostly on the performance of multiplier thus multipliers should be fast and …
[PDF][PDF] A Digital CMOS Parallel Counter Architecture for Frequency Divider Based on Transmission Gate Logic
AK Choudhary, KP Patra - academia.edu
VLSI fabrication technology is still in the process of evolution which is leading to smaller line
widths and feature size and to higher packing density of circuitry on a chip. The scaling …
widths and feature size and to higher packing density of circuitry on a chip. The scaling …
[PDF][PDF] Design of Area optimized High Speed Adder Circuits in Self Resetting Logic Style
MK Kalaiselvi, H Mangalam, MK Manjunathan - researchgate.net
Dynamic logic families offer good performance over traditional CMOS logic. This is due to
the comparatively high noise margins coupled with the ease of implementation. The main …
the comparatively high noise margins coupled with the ease of implementation. The main …
Two phase nonoverlap** clocked All-N-Logic in subthreshold region with 49fJ power delay product
M Kargar… - The 16th CSI International …, 2012 - ieeexplore.ieee.org
This paper represents a new structure of ANL logic, named TPSANL to achieve ultra low
power with no glitches in the subthreshold region. Since different ANL logics suffer from …
power with no glitches in the subthreshold region. Since different ANL logics suffer from …
[CITA][C] DESIGN & ANALYSIS OF 4-BIT COUNTER USING SUB-MICRON TECHNOLOGY
M ManishaRahamatkar, M MittalPisalkar…