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Self-aligned trench silicide process for preventing gate contact to silicide shorts
VS Basker, K Cheng - US Patent 9,722,043, 2017 - Google Patents
(57) ABSTRACT A method of forming a finFET device includes forming a plurality offins on a
Substrate; forming a plurality of dummy gate structures over the plurality of fins, the dummy …
Substrate; forming a plurality of dummy gate structures over the plurality of fins, the dummy …
Self aligned contact with improved robustness
(57) ABSTRACT A method of forming a semiconductor device including pro viding a
functional gate structure on a channel portion of a semiconductor Substrate. A gate sidewall …
functional gate structure on a channel portion of a semiconductor Substrate. A gate sidewall …
Hybrid logic and SRAM contacts
VS Basker, K Cheng, A Khakifirooz - US Patent 10,083,972, 2018 - Google Patents
Primary Examiner—Mohsen Ahmadi (74) Attorney, Agent, or Firm—Michael O'Keefe (57)
ABSTRACT The method includes forming a first opening in a dielectric layer exposing a …
ABSTRACT The method includes forming a first opening in a dielectric layer exposing a …
Self aligned contact with improved robustness
US9105606B2 - Self aligned contact with improved robustness - Google Patents US9105606B2
- Self aligned contact with improved robustness - Google Patents Self aligned contact with …
- Self aligned contact with improved robustness - Google Patents Self aligned contact with …
Minimizing shorting between FinFET epitaxial regions
K Cheng, B Pranatharthiharan, A Reznicek… - US Patent …, 2016 - Google Patents
The present invention relates generally to semiconductors, and more particularly, to a
structure and method of mini mizing shorting between epitaxial regions in Small pitch fin …
structure and method of mini mizing shorting between epitaxial regions in Small pitch fin …
Minimizing shorting between FinFET epitaxial regions
K Cheng, B Pranatharthiharan, A Reznicek… - US Patent …, 2017 - Google Patents
The present invention relates generally to semiconductors, and more particularly, to a
structure and method of mini mizing shorting between epitaxial regions in Small pitch fin …
structure and method of mini mizing shorting between epitaxial regions in Small pitch fin …
Minimizing shorting between FinFET epitaxial regions
K Cheng, B Pranatharthiharan, A Reznicek… - US Patent …, 2018 - Google Patents
According to an embodiment, a method of physically separating epitaxial regions in fin field
effect transistors (FinFETs) is disclosed. The method may include: forming a dielectric region …
effect transistors (FinFETs) is disclosed. The method may include: forming a dielectric region …
Hybrid logic and SRAM contacts
VS Basker, K Cheng, A Khakifirooz - US Patent 9,570,450, 2017 - Google Patents
BACKGROUND The present invention generally relates to semiconductor manufacturing,
and more particularly to fabricating electri cally insulated contacts of a logic device and a …
and more particularly to fabricating electri cally insulated contacts of a logic device and a …
Minimizing shorting between FinFET epitaxial regions
K Cheng, B Pranatharthiharan, A Reznicek… - US Patent …, 2017 - Google Patents
The present invention relates generally to semiconductors, and more particularly, to a
structure and method of mini mizing shorting between epitaxial regions in small pitch fin field …
structure and method of mini mizing shorting between epitaxial regions in small pitch fin field …
Semiconductor structure with metal cap layer
CL Cheng, Z Fang - US Patent 11,393,912, 2022 - Google Patents
Semiconductor structures and method for forming the same are provided. The
semiconductor structure includes a fin protruding from a substrate and a gate stack formed …
semiconductor structure includes a fin protruding from a substrate and a gate stack formed …