In this paper, we report about the derivation of a physics-based compact model of random
telegraph noise (RTN) in HfO 2-based resistive random access memory (RRAM) devices …

It has been demonstrated that the introduction of HfO 2/TiN gate stacks into CMOS
technologies provides the means to continue with traditional device gate length scaling …

This paper reviews the evolution of the charge pum** (CP) technique and its applications
from the micrometer-scale to the atomic-scale device era. We describe the more significant …

The availability of on-chip non-volatile memory for advanced high-k-metal-gate CMOS
technology nodes has been limited due to integration and scaling challenges as well as …

The stress-induced leakage current (SILC) in nFETs with SiO 2/HfO 2/TiN dual-dielectric
gate stacks with metal electrodes is studied during positive-bias temperature stress at high …

Based on the vast perusal, an overview on the negative bias temperature instability (NBTI)
effect in metal oxide semiconductor (MOS) devices, from different perspectives as well as …

In this letter, charge trap** behavior in 22-nm technology high-k-metal-gate SOI CMOS
logic devices is analyzed under various bias stress and self-heating conditions. It is …

Positive bias temperature instability (PBTI) is poised to cause significant degradation to
nFETs with deep scaling into nanometers. It is commonly modeled by a power law fitted with …

Dielectric breakdown is one of the key failure mechanisms in front-end silicon-based
complementary metal oxide semiconductor (CMOS) technology. With the advent of HfO 2 …

Instability of InGaAs channel nMOSFETs with the Al 2 O 3/ZrO 2 gate stack under positive
bias stress demonstrates recoverable and unrecoverable components, which can be …