Cache telepathy: Leveraging shared resource attacks to learn {DNN} architectures
Deep Neural Networks (DNNs) are fast becoming ubiquitous for their ability to attain good
accuracy in various machine learning tasks. A DNN's architecture (ie, its hyperparameters) …
accuracy in various machine learning tasks. A DNN's architecture (ie, its hyperparameters) …
Practical near-data processing for in-memory analytics frameworks
The end of Dennard scaling has made all systemsenergy-constrained. For data-intensive
applications with limitedtemporal locality, the major energy bottleneck is data …
applications with limitedtemporal locality, the major energy bottleneck is data …
A deeper look into rowhammer's sensitivities: Experimental analysis of real dram chips and implications on future attacks and defenses
RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (ie,
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
[LLIBRE][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stop** your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in
which accesses interact with the “3-D” structure of banks, rows, and columns characteristic of …
which accesses interact with the “3-D” structure of banks, rows, and columns characteristic of …
[LLIBRE][B] Computer systems: a programmer's perspective
RE Bryant, DR O'Hallaron - 2011 - thuvienso.hoasen.edu.vn
Computer Systems: A Programmer's Perspective Page 1 Computer Systems A Programmer’s
Perspective Randal E. Bryant Carnegie Mellon University David R. O’Hallaron Carnegie Mellon …
Perspective Randal E. Bryant Carnegie Mellon University David R. O’Hallaron Carnegie Mellon …
Scheduling techniques for GPU architectures with processing-in-memory capabilities
Processing data in or near memory (PIM), as opposed to in conventional computational units
in a processor, can greatly alleviate the performance and energy penalties of data transfers …
in a processor, can greatly alleviate the performance and energy penalties of data transfers …
[LLIBRE][B] Reconfigurable computing: the theory and practice of FPGA-based computation
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap
between the separate worlds of hardware and software design—the key feature of …
between the separate worlds of hardware and software design—the key feature of …
Self-optimizing memory controllers: A reinforcement learning approach
Efficiently utilizing off-chip DRAM bandwidth is a critical issuein designing cost-effective,
high-performance chip multiprocessors (CMPs). Conventional memory controllers deliver …
high-performance chip multiprocessors (CMPs). Conventional memory controllers deliver …
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance
Emerging GPGPU architectures, along with programming models like CUDA and OpenCL,
offer a cost-effective platform for many applications by providing high thread level …
offer a cost-effective platform for many applications by providing high thread level …