The future transistors

W Cao, H Bu, M Vinet, M Cao, S Takagi, S Hwang… - Nature, 2023 - nature.com
The metal–oxide–semiconductor field-effect transistor (MOSFET), a core element of
complementary metal–oxide–semiconductor (CMOS) technology, represents one of the …

Limits on fundamental limits to computation

IL Markov - Nature, 2014 - nature.com
An indispensable part of our personal and working lives, computing has also become
essential to industries and governments. Steady improvements in computer hardware have …

[LIVRE][B] Computational Electronics: semiclassical and quantum device modeling and simulation

D Vasileska, SM Goodnick, G Klimeck - 2017 - books.google.com
Starting with the simplest semiclassical approaches and ending with the description of
complex fully quantum-mechanical methods for quantum transport analysis of state-of-the …

Process technology variation

KJ Kuhn, MD Giles, D Becher, P Kolar… - … on Electron Devices, 2011 - ieeexplore.ieee.org
Moore's law technology scaling has improved performance by five orders of magnitude in
the last four decades. As advanced technologies continue the pursuit of Moore's law, a …

Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

A Asenov, S Kaya, AR Brown - IEEE Transactions on Electron …, 2003 - ieeexplore.ieee.org
In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the
gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep …

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

A Asenov, AR Brown, JH Davies, S Kaya… - IEEE transactions on …, 2003 - ieeexplore.ieee.org
Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an
increasingly important role when semiconductor devices are scaled to decananometer and …

Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS

KJ Kuhn - 2007 IEEE International Electron Devices Meeting, 2007 - ieeexplore.ieee.org
This paper presents an overview of process variation effects, including examples of
mitigation strategies and test methods. Experimental and theoretical comparisons are …

Machine learning approach for predicting the effect of statistical variability in Si junctionless nanowire transistors

H Carrillo-Nuñez, N Dimitrova… - IEEE Electron …, 2019 - ieeexplore.ieee.org
This letter investigates the possibility to replace numerical TCAD device simulations with a
multi-layer neural network (NN). We explore if it is possible to train the NN with the required …

Electrostatic do** in semiconductor devices

G Gupta, B Rajasekharan… - IEEE transactions on …, 2017 - ieeexplore.ieee.org
To overcome the limitations of chemical do** in nanometer-scale semiconductor devices,
electrostatic do** (ED) is emerging as a broadly investigated alternative to provide …

Managing Process Variation in Intel's 45nm CMOS Technology.

K Kuhn, C Kenyon, A Kornfeld, M Liu… - Intel Technology …, 2008 - search.ebscohost.com
The key message of this paper is that process variation is not an insurmountable barrier to
Moore's Law, but is simply another challenge to be overcome. This message is illustrated …