Demystifying cxl memory with genuine cxl-ready systems and devices
The ever-growing demands for memory with larger capacity and higher bandwidth have
driven recent innovations on memory expansion and disaggregation technologies based on …
driven recent innovations on memory expansion and disaggregation technologies based on …
The virtual block interface: A flexible alternative to the conventional virtual memory framework
Computers continue to diversify with respect to system designs, emerging memory
technologies, and application memory demands. Unfortunately, continually adapting the …
technologies, and application memory demands. Unfortunately, continually adapting the …
Merchandiser: Data placement on heterogeneous memory for task-parallel hpc applications with load-balance awareness
Z ** a multicore platform utilizing open RISC-V cores
H Jang, K Han, S Lee, JJ Lee, SY Lee, JH Lee… - IEEE …, 2021 - ieeexplore.ieee.org
RISC-V has been experiencing explosive growth since its first appearance in 2011. Dozens
of free and open cores developed based on this instruction set architecture have been …
of free and open cores developed based on this instruction set architecture have been …
Asymmetric resilience: Exploiting task-level idempotency for transient error recovery in accelerator-based systems
Accelerators make the task of building systems that are re-silient against transient errors like
voltage noise and soft errors hard. Architects integrate accelerators into the system as black …
voltage noise and soft errors hard. Architects integrate accelerators into the system as black …
Minotaur: Adapting software testing techniques for hardware errors
With the end of conventional CMOS scaling, efficient resiliency solutions are needed to
address the increased likelihood of hardware errors. Silent data corruptions (SDCs) are …
address the increased likelihood of hardware errors. Silent data corruptions (SDCs) are …
HaRMony: Heterogeneous-reliability memory and QoS-aware energy management on virtualized servers
The explosive growth of data increases the storage needs, especially within servers, making
DRAM responsible for more than 40% of the total system power. Such a reality has made …
DRAM responsible for more than 40% of the total system power. Such a reality has made …
Composite-ISA cores: Enabling multi-ISA heterogeneity using a single ISA
Heterogeneous multicore architectures are comprised of multiple cores of different sizes,
organizations, and capabilities. These architectures maximize both performance and energy …
organizations, and capabilities. These architectures maximize both performance and energy …
Dstress: Automatic synthesis of dram reliability stress viruses using genetic algorithms
L Mukhanov, DS Nikolopoulos… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
Failures become inevitable in DRAM devices, which is a major obstacle for scaling down the
density of cells in future DRAM technologies. These failures can be detected by specific …
density of cells in future DRAM technologies. These failures can be detected by specific …
Survey of memory management techniques for hpc and cloud computing
A Pupykina, G Agosta - IEEE Access, 2019 - ieeexplore.ieee.org
The emergence of new classes of HPC applications and usage models, such as real-time
HPC and cloud HPC, coupled with the increasingly heterogeneous nature of HPC …
HPC and cloud HPC, coupled with the increasingly heterogeneous nature of HPC …