A survey of coarse-grained reconfigurable architecture and design: Taxonomy, challenges, and applications

L Liu, J Zhu, Z Li, Y Lu, Y Deng, J Han, S Yin… - ACM Computing …, 2019 - dl.acm.org
As general-purpose processors have hit the power wall and chip fabrication cost escalates
alarmingly, coarse-grained reconfigurable architectures (CGRAs) are attracting increasing …

Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks

YH Chen, J Emer, V Sze - ACM SIGARCH computer architecture news, 2016 - dl.acm.org
Deep convolutional neural networks (CNNs) are widely used in modern AI systems for their
superior accuracy but at the cost of high computational complexity. The complexity comes …

Plasticine: A reconfigurable architecture for parallel paterns

R Prabhakar, Y Zhang, D Koeplinger… - ACM SIGARCH …, 2017 - dl.acm.org
Reconfigurable architectures have gained popularity in recent years as they allow the
design of energy-efficient accelerators. Fine-grain fabrics (eg FPGAs) have traditionally …

Spatial: A language and compiler for application accelerators

D Koeplinger, M Feldman, R Prabhakar… - Proceedings of the 39th …, 2018 - dl.acm.org
Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for
improved performance and energy efficiency. Unfortunately, adoption of these architectures …

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules

A Farmahini-Farahani, JH Ahn… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
Energy consumed for transferring data across the processor memory hierarchy constitutes a
large fraction of total system energy consumption, and this fraction has steadily increased …

Using dataflow to optimize energy efficiency of deep neural network accelerators

YH Chen, J Emer, V Sze - IEEE Micro, 2017 - ieeexplore.ieee.org
The authors demonstrate the key role dataflows play in the optimization of energy efficiency
for deep neural network (DNN) accelerators. By introducing a systematic approach to …

MachSuite: Benchmarks for accelerator design and customized architectures

B Reagen, R Adolf, YS Shao, GY Wei… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
Recent high-level synthesis and accelerator-related architecture papers show a great
disparity in workload selection. To improve standardization within the accelerator research …

Stream-dataflow acceleration

T Nowatzki, V Gangadhar, N Ardalani… - Proceedings of the 44th …, 2017 - dl.acm.org
Demand for low-power data processing hardware continues to rise inexorably. Existing
programmable and" general purpose" solutions (eg. SIMD, GPGPUs) are insufficient, as …

Dsagen: Synthesizing programmable spatial accelerators

J Weng, S Liu, V Dadu, Z Wang, P Shah… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
Domain-specific hardware accelerators can provide orders of magnitude speedup and
energy efficiency over general purpose processors. However, they require extensive manual …

Fifer: Practical acceleration of irregular applications on reconfigurable architectures

QM Nguyen, D Sanchez - MICRO-54: 54th Annual IEEE/ACM …, 2021 - dl.acm.org
Coarse-grain reconfigurable arrays (CGRAs) can achieve much higher performance and
efficiency than general-purpose cores, approaching the performance of a specialized design …