This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …

This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …

This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …

In this article, a two-stage millimeter (mm)-wave frequency synthesizer with low in-band
noise and robust locking reference-sampling techniques is presented. Using a two-stage …

This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …

This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-
μW ultra-lowpower operation. The proposed switching feedback can seamlessly change the …

A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-
antenna transceivers is presented. The system is modular with one phase locked loop (PLL) …

This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with
scalable power consumption, which achieves an figure of merit (FOM) of-246 dB. The …

An active-mixer-adopted sub-sampling phase-locked loop (AMASS-PLL) is presented that
replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub …

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL
(SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low …