This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold
region that improves read, write, and hold stability. While at low voltages, the write-ability is …

In order to meet the ultra-low power requirement of modern digital systems, voltage scaling
is a fruitful technique that is widely adopted. However, the voltage scaling at ultra-scaled …

This brief presents SRAM write assist circuit using cell supply voltage self-collapse with
bitline charge sharing (SC-BCS) that can lower the minimum operating voltage to the near …

In this article, we present static random access memory (SRAM) write-and performance-
assist cells (W-and P-ACs, respectively) that can effectively resolve the degradation in …

Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-
/energy-constrained edge devices due to the strong voltage scaling capability, fast design …

In low supply voltage (), the wordline (WL) underdrive read assist and the negative bitline
(NBL) write assist circuits are widely used for stable operation of SRAM. However, NBL …

Wide input-output (IO) chip-to-chip interfaces, such as 3-D chip stacking [through-silicon via
(TSV)], silicon interposer in high-bandwidth memory (HBM), and other 2.5-D chip-to-chip …

Write assists (WAs), such as negative bitline and collapse supply voltage (VDD), can
effectively improve the write V min of static random access memory (SRAM) cells. The …

The energy efficiency of IoT devices must be improved to improve their computation
performance owing to the advancements in IoT technology. In this study, we present a …

This paper proposes a bitline charge sharing suppressed bitline read assist (BCS RA) and a
cell supply collapse write assist (BCS WA). The proposed BCS RA suppresses the bitline …