[BOOK][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
A set of benchmarks for modular testing of SOCs
EJ Marinissen, V Iyengar… - Proceedings …, 2002 - ieeexplore.ieee.org
This paper presents the ITC'02 SOC test benchmarks. The purpose of this new benchmark
set is to stimulate research into new methods and tools for modular testing of SOCs and to …
set is to stimulate research into new methods and tools for modular testing of SOCs and to …
Task scheduling–review of algorithms and analysis of potential use in a biological wastewater treatment plant
The idea of task scheduling is to increase the efficiency of a system by minimising wasted
time, evenly loading machines, or maximising the throughput of machines. Moreover, the …
time, evenly loading machines, or maximising the throughput of machines. Moreover, the …
A unified approach to reduce SOC test data volume, scan power and testing time
A Chandra, K Chakrabarty - IEEE transactions on computer …, 2003 - ieeexplore.ieee.org
We present a test resource partitioning (TRP) technique that simultaneously reduces test
data volume, test application time, and scan power. The proposed approach is based on the …
data volume, test application time, and scan power. The proposed approach is based on the …
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes
A Chandra, K Chakrabarty - Proceedings of the 39th annual design …, 2002 - dl.acm.org
We present a test resource partitioning (TRP) technique that simultaneously reduces test
data volume, test application time and scan power. The proposed approach is based on the …
data volume, test application time and scan power. The proposed approach is based on the …
[PDF][PDF] Test scheduling of core based system-on-chip using modified ant colony optimization
G Chandrasekaran, V Kumarasamy… - Journal Européen des …, 2019 - academia.edu
Accepted: 25 November 2019 A System-on-Chip (SoC) is an integrated circuit that combines
various electronic components in a single die. The SoC components mostly involve user …
various electronic components in a single die. The SoC components mostly involve user …
A novel local search for unicost set covering problem using hyperedge configuration checking and weight diversity
Y Wang, D Ouyang, L Zhang… - Science China …, 2017 - search.proquest.com
The unicost version of well-known set covering problem (SCP) is central to a wide variety of
practical applications for which finding an optimal solution quickly is crucial. In this paper, we …
practical applications for which finding an optimal solution quickly is crucial. In this paper, we …
SOC test scheduling using simulated annealing
We propose an SOC test scheduling method based on simulated annealing. In our method,
the test scheduling is formulated as a two-dimensional bin packing problem (rectangle …
the test scheduling is formulated as a two-dimensional bin packing problem (rectangle …
Resource allocation and test scheduling for concurrent test of core-based SOC design
A method to solve the resource allocation and test scheduling problems together in order to
achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this …
achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this …
On IEEE P1500's standard for embedded core test
EJ Marinissen, R Kapur, M Lousberg… - SOC (System-on-a-Chip …, 2002 - Springer
The increased usage of embedded pre-designed reusable cores necessitates a core-based
test strategy, in which cores are tested as separate entities IEEE P1500 Standard for …
test strategy, in which cores are tested as separate entities IEEE P1500 Standard for …