Multiply accumulate operations in memristor crossbar arrays for analog computing

J Chen, J Li, Y Li, X Miao - Journal of Semiconductors, 2021‏ - iopscience.iop.org
Memristors are now becoming a prominent candidate to serve as the building blocks of non-
von Neumann in-memory computing architectures. By map** analog numerical matrices …

RETRACTED ARTICLE: A nano-scale design of a multiply-accumulate unit for digital signal processing based on quantum computing

SS Ahmadpour, NJ Navimipour, S Yalcin… - Optical and Quantum …, 2024‏ - Springer
Digital signal processing (DSP) is used in computer processing to conduct different signal-
processing tasks. The DSPs are used in the series numbers representing a continuous …

A high-performance multiply-accumulate unit by integrating additions and accumulations into partial product reduction process

CW Tung, SH Huang - Ieee Access, 2020‏ - ieeexplore.ieee.org
In this paper, we propose a low-power high-speed pipeline multiply-accumulate (MAC)
architecture. In a conventional MAC, carry propagations of additions (including additions in …

Exploring the Use of DNS as a Search Engine for the Web of Things

A Kamilaris, K Papakonstantinou… - 2014 IEEE World …, 2014‏ - ieeexplore.ieee.org
Sensor technology is becoming pervasive in our everyday lives, measuring the real world
around us. The Internet of Things enables sensor devices to become active citizens of the …

A high-speed, energy-efficient two-cycle multiply-accumulate (MAC) architecture and its application to a double-throughput MAC unit

TT Hoang, M Själander… - IEEE Transactions on …, 2010‏ - ieeexplore.ieee.org
We propose a high-speed and energy-efficient two-cycle multiply-accumulate (MAC)
architecture that supports two's complement numbers, and includes accumulation guard bits …

[PDF][PDF] Sensor less Control of BLDC Motor using Fuzzy logic controller for Solar power Generation

A Sundaram, GP Ramesh - International Journal of MC Square …, 2017‏ - researchgate.net
Brushless dc (BLDC) motors are electronic controlled and have the rotor position for
commutating the stator winding current. This paper presents the BLDC motor sensor less …

[PDF][PDF] Implementation of area optimized low power multiplication and accumulation

SC Venkateswarlu, NU Kumar, NS Kumar… - International Journal of …, 2019‏ - academia.edu
There is number of computations involved at every stage in Digital Signal Processing (DSP).
At every stage of computation we have addition and multiplication of the terms derived from …

Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology

N Kandasamy, F Ahmad, S Reddy, N Telagam… - Microprocessors and …, 2018‏ - Elsevier
This paper presents the high-speed adder circuit design based on 18 transistor (18T) full
swing gate diffusion input based logic gates and transmission based techniques to compute …

Design of MAC unit for digital filters in signal processing and communication

B Harish, MSS Rukmini, K Sivani - International Journal of Speech …, 2022‏ - Springer
Digital signal processors (DSP) the endless requirement is the development of ability in
processors to hold the difficulties resulted in the assimilation of CPU cores in a particular IC …

Design of all-optical parallel multipliers using semiconductor optical amplifier-based Mach–Zehnder interferometers

S Sharma, S Roy - The Journal of Supercomputing, 2021‏ - Springer
Due to the benefits of low power, high bandwidth and complementary metal-oxide-
semiconductor (CMOS) compatibility, the design of optical circuits has spurred great …