As the interconnect delay exceeds the gate delay, the integrated circuit (IC) technology has
evolved from a transistor-centric era to an interconnect-centric era. Conventional metallic …

Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more
than twice as much new content, adding the latest developments in circuit models …

Several interesting topologies emerge by incorporating the third dimension in networks-on-
chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC …

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Interconnect has become a primary bottleneck in integrated circuit design. As CMOS
technology is scaled, it will become increasingly difficult for conventional copper …

A closed-form expression for estimation of the 50% time delay and an empirical formula for
the optimal number of repeaters to minimize the total time delay in a single multiwall carbon …

The increasing viability of three dimensional (3D) silicon integration technology has opened
new opportunities for chip design innovations, including the prospect of extending emerging …

Synchronous parallel links are widely used in modern VLSI designs for on-chip inter-module
communication. Long range parallel links occupy large area and incur high capacitive load …

This textbook comprehensively covers on-chip interconnect dimension and application of
carbon nanomaterials for modeling VLSI interconnect and buffer circuits. It provides analysis …

Optimal repeater designs are performed for Cu and carbon nanotube (CNT)-based
nanointerconnects to reduce the delay and power dissipation. The effects of inductance and …