Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic

S Vakili, JMP Langlois, G Bois - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
Bit-width allocation has a crucial impact on hardware efficiency and accuracy of fixed-point
arithmetic circuits. This paper introduces a new accuracy-guaranteed word-length …

Towards hardware IIR filters computing just right: Direct form I case study

A Volkova, M Istoan, F De Dinechin… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Linear Time Invariant (LTI) filters are often specified and simulated using high-precision
software, before being implemented in low-precision fixed-point hardware. A problem is that …

LVQ neural network optimized implementation on FPGA devices with multiple-wordlength operations for real-time systems

AG Blaiech, K Ben Khalifa, M Boubaker… - Neural Computing and …, 2018 - Springer
The development of hardware platforms for artificial neural networks (ANN) has been
hindered by the high consumption of power and hardware resources. In this paper, we …

Optimization of signal processing applications using parameterized error models for approximate adders

C Dharmaraj, V Vasudevan… - ACM Transactions on …, 2021 - dl.acm.org
Approximate circuit design has gained significance in recent years targeting error-tolerant
applications. In the literature, there have been several attempts at optimizing the number of …

Arithmetic approaches for rigorous design of reliable Fixed-Point LTI filters

A Volkova, T Hilaire, C Lauter - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
In this paper we target the Fixed-Point (FxP) implementation of Linear Time-Invariant (LTI)
filters evaluated with statespace equations. We assume that wordlengths are fixed and that …

A formal method for optimal high-level casting of heterogeneous fixed-point adders and subtractors

R Sierra, C Carreras, G Caffarena… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Fixed-point arithmetic datapaths with heterogeneous scaling and wordlengths are
commonplace in resource, latency, or power constrained designs. This paper describes and …

GPU-accelerated high-level synthesis for bitwidth optimization of FPGA datapaths

N Kapre, D Ye - Proceedings of the 2016 ACM/SIGDA International …, 2016 - dl.acm.org
Bitwidth optimization of FPGA datapaths can save hardware resources by choosing the
fewest number of bits required for each datapath variable to achieve a desired quality of …

Data-types optimization for floating-point formats by program transformation

N Damouche, M Martel… - … Conference on Control …, 2016 - ieeexplore.ieee.org
In floating-point arithmetic, a desirable property of computations is to be accurate, since in
many industrial context small or large perturbations due to round-off errors may cause …

[PDF][PDF] Hai-Nam NGUYEN

ÉPIC Lannion - 2012 - academia.edu
L'évolution des technologies des circuits intégrés permet d'implanter au sein des systemes
embarqués de nouvelles applications, plus complexes, pour le traitement du signal, de …

Recurrent deep neural learning classification algorithm based high level synthesis in VLSI circuit with runtime adaptability

M Thillai Rani, KP Sai Pradeep… - Journal of Intelligent …, 2022 - content.iospress.com
Electronics industry has attained huge development in last few decades due to the rapid
increase in system design applications. With the growth of very large scale integration (VLSI) …