After two decades of intensive development, 3-D integration has proven invaluable for
allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink …

As a powerful enabling technology, three-dimensional (3D) integration, which uses wafer
bonding to integrate multiple wafers in the vertical direction and uses through‑silicon-vias …

Vacuum and hermetic packaging is a critical requirement for optimal performance of many
micro-electromechanical systems (MEMS), vacuum electronics, and quantum devices …

Advancements in miniaturisation and new capabilities of implantable devices impose a
need for the development of compact, hermetic, and CMOS-compatible micro packaging …

Reliability risks for two different types of through-silicon-vias (TSVs) are discussed in this
paper. The first is a partially-filled copper TSV, if which the copper layer covers the side walls …

This paper presents the fabrication of wafer-level hermetic encapsulation for MEMS devices
using low-temperature (300° C) Au-Sn bonding together with their pre-and postbonding …

This paper presents a 0-level packaging technology for (RF-) MEMS implementing vertical
feedthroughs or through-Si-via's (TSVs) and metal bonding. A thinned cap** substrate …

Abstract In this work, Au–Sn eutectic bonding and Au–Sn thermo-compression bonding are
studied for applications in hermetic packaging at wafer level. Eutectic bonding experiments …

Au–Au‐bonding‐based wafer‐level vacuum packaging technology using in‐plane
feedthrough of thick Au signal lines was developed for high‐frequency micro …

Gold-Tin eutectic bonding was studied to get hermetic packaging at wafer level. Scanning
Electron Microscopy cross section images showed the sealing joint morphology at different …