Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices,
which typically rely on reduced memory footprint and low-performance processors. While …

Transient hardware faults during the execution of a program can cause data corruptions. We
present HAFT, a fault tolerance technique using hardware extensions of commodity CPUs to …

Systems and methods for implementing a lightweight check point technique for resilience
against soft errors are dis closed. The technique provides effective, safe, and timely soft error …

Future cyber-physical systems are expected to be dynamic, evolving while already being
deployed. Frequent updates of software components are likely to become the norm even for …

Existing software development methodologies mostly assume that an application runs on a
single device without concern about the non-functional requirements of an embedded …

Accelerators make the task of building systems that are re-silient against transient errors like
voltage noise and soft errors hard. Architects integrate accelerators into the system as black …

Soft errors are considered as the main reliability challenge for sub-nanoscale
microprocessors. Software-level soft error resilience schemes are desirable because they …

Instruction-Level Redundancy (ILR) is a well-known approach to tolerate transient CPU
faults. It replicates instructions in a program and inserts periodic checks to detect and correct …

Soft error rates in processors have been increasing with decreasing feature size and larger
chips. Software-only solutions have been proposed to deal with this problem, for instance …

Modern informatics based systems are mostly composed from self-contained components.
To be useful for really big systems, composed of many components, proper abstraction …