Optimization techniques for CNT based VLSI interconnects—a review

A Karthikeyan, PS Mallick - Journal of Circuits, Systems and …, 2017 - World Scientific
Interconnects plays an important role in integrated circuits. Copper is used as an
interconnect material, but beyond 22 nm technology node it faces many problems due to …

Comprehensive stochastic analysis method for tree-type PDNs and ground pollution on mixed-signal PCBs

M Mehri - Scientia Iranica, 2024 - scientiairanica.sharif.edu
In this paper, a stochastic analysis method is proposed for extraction and evaluation of
power distribution map (PDM) in system printed circuit board (PCB). This is conducted …

High-speed and low-power repeater for VLSI interconnects

A Karthikeyan, PS Mallick - Journal of Semiconductors, 2017 - iopscience.iop.org
This paper proposes a repeater for boosting the speed of interconnects with low power
dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay …

An analytical model for the CMOS inverter

P Chaourani, I Messaris, N Fasarakis… - … Workshop on Power …, 2014 - ieeexplore.ieee.org
A new analytical model for the CMOS inverter is introduced. This model results by solving
analytically the differential equation which describes the inverter operation. It uses new …

Statistical prediction of planar power consumption distribution in digital system layout/PCB

S Heidari, M Mehri, N Masoumi - 2017 IEEE 21st Workshop on …, 2017 - ieeexplore.ieee.org
In this paper, a statistical approach is proposed for estimation of power consumption
distribution in the layout/PCB of digital systems. The power spectrum density for a buffer is …

A unified CMOS inverter model for planar and FinFET nanoscale technologies

P Chaourani, S Nikolaidis - 17th International Symposium on …, 2014 - ieeexplore.ieee.org
In this paper, a new analytical model for describing the output waveform of the CMOS
inverter for planar and FinFET nanoscale technologies, is introduced. A modified expression …

Improving analytical delay modeling for CMOS inverters

FS Marranghello, RP Ribas, AI Reis - … . Porto Alegre. Vol. 10, no. 2 …, 2015 - lume.ufrgs.br
Analytical methods for gate delay estimation are very useful to speedup timing analysis of
digital integrated circuits. This work presents a novel approach to analytically estimate the …

VLSI interconnect issues in definitive and stochastic environments

M Mehri, R Sarvari, MHM Kouhani, Z Shariati - Microelectronics Journal, 2015 - Elsevier
A system designer needs to estimate the behavior of a system interconnection based on
different patterns of switching which happen around an interconnect. Two different scenarios …

[PDF][PDF] DESIGN LOW POWER PERFORMANCE PROPOSED FULL-ADDER ARCHITECTURE

VSAI KRISHNA, KSN CHANDRA - Journal of Nonlinear Analysis and …, 2024 - jnao-nu.com
Full adder is an essential component for the design and development of all types of
processor. This is widely used to implement Full Adder (FA) circuits. Performance of FA in …

[PDF][PDF] DESIGN OF HIGH EFFICIENT AND HIGH SPEED PARALLEL PREFIX MULTIPLIER

N Nagaraju, M Tech, R Miste, ISS Sajana, VN Vamsi… - jnao-nu.com
Decimal computation is highly demanded in many human-centric applications such as
banking, accounting, tax calculation, and currency conversion. Hence the design and …